mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
846bfa3357
-adding reset signals to synchronizer to solve startup issues -setting config in test bench for speedup, default reg config now correct -fix (my) stupid bug in etx_arbiter -adding reset to fifo (todo: review this!) -reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
119 lines
3.8 KiB
Verilog
119 lines
3.8 KiB
Verilog
// ###############################################################
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// # FUNCTION: Synchronous clock divider that divides by integer
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// ###############################################################
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module clock_divider(/*AUTOARG*/
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// Outputs
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clkout, clkout90,
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// Inputs
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clkin, divcfg, reset
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);
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input clkin; // Input clock
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input [3:0] divcfg; // Divide factor
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input reset; // Counter init
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output clkout; // Divided clock phase aligned with clkin
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output clkout90; // Divided clock with 90deg phase shift with clkout
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reg clkout_reg;
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reg [7:0] counter;
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reg [7:0] divcfg_dec;
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wire div2_sel;
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wire div1_sel;
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wire posedge_match;
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wire negedge_match;
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wire posedge90_match;
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wire negedge90_match;
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wire clkout90_div2_in;
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wire clkout90_div4_in;
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reg clkout90_div4;
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reg clkout90_div2;
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// ###################
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// # Decode divcfg
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// ###################
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always @ (divcfg[3:0])
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casez (divcfg[3:0])
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4'b0110 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
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4'b0101 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
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4'b0100 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
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4'b0011 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
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4'b0010 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
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4'b0001 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
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4'b0000 : divcfg_dec[7:0] = 8'b10000000; // Divide by 128
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default : divcfg_dec[7:0] = 8'b0000000; // others
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endcase
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//Divide by two special case
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assign div2_sel = divcfg[3:0]==4'b0110;
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assign div1_sel = divcfg[3:0]==4'b0111;
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always @ (posedge clkin or posedge reset)
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if(reset)
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counter[7:0] <= 8'b000001;
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else
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if(posedge_match)
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counter[7:0] <= 8'b000001;// Self resetting
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else
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counter[7:0] <= (counter[7:0] + 8'b000001);
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assign posedge_match = (counter[7:0]==divcfg_dec[7:0]);
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assign negedge_match = (counter[7:0]=={1'b0,divcfg_dec[7:1]});
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assign posedge90_match = (counter[7:0]==({2'b00,divcfg_dec[7:2]}));
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assign negedge90_match = (counter[7:0]==({2'b00,divcfg_dec[7:2]} +
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{1'b0,divcfg_dec[7:1]}));
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always @ (posedge clkin or posedge reset)
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if(reset)
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clkout_reg <= 1'b0;
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else if(posedge_match)
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clkout_reg <= 1'b1;
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else if(negedge_match)
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clkout_reg <= 1'b0;
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assign clkout = div1_sel ? clkin : clkout_reg;
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assign clkout90_div4_in = posedge90_match ? 1'b1 :
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negedge90_match ? 1'b0 :
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clkout90_div4;
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assign clkout90_div2_in = negedge_match ? 1'b1 :
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posedge_match ? 1'b0 :
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clkout90_div2;
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always @ (posedge clkin)
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clkout90_div4 <= clkout90_div4_in;
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always @ (negedge clkin)
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clkout90_div2 <= clkout90_div2_in;
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assign clkout90 = div2_sel ? clkout90_div2 : clkout90_div4;
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endmodule // clock_divider
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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