Andreas Olofsson b1a9f502ca Xilinx models ...

-adding ODDR model
-configuring the ecfg (rx/tx/clk) in testbench

2015-04-15 17:54:19 -04:00

..

dv_ecfg.v

Cleanup

2015-04-11 00:12:57 -04:00

dv_elink_tb.v

Xilinx models

2015-04-15 17:54:19 -04:00

dv_elink.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00

elink.cmd

Running with "TARGET_CLEAN"

2015-04-14 23:48:58 -04:00

run.sh

Verilator lint cleanup

2015-04-14 14:00:23 -04:00