Andreas Olofsson dcdf4a9231 Adding experimental OSERDESE2 model ...

Experimental model, dirty design
Bits are coming out and frame looks good..
Will continue with RX and debugging tomorrow

2015-04-15 23:03:33 -04:00

..

ecfg.v

Cleaning up tx config register

2015-04-15 17:53:50 -04:00

eclocks.v

Adding experimental OSERDESE2 model

2015-04-15 23:03:33 -04:00

elink_regmap.v

Reorganizing files...too many folders after all.

2015-04-11 00:10:16 -04:00

elink.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00

emaxi.v

AXI bug fixes

2015-04-14 20:26:58 -04:00

ereset.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00

erx_disty.v

Man that's a lot of yak shaving....

2015-04-13 23:35:21 -04:00

erx_io.v

Verilator lint cleanup

2015-04-14 14:00:23 -04:00

erx_protocol.v

Verilator lint cleanup

2015-04-14 14:00:23 -04:00

erx.v

Verilator lint cleanup

2015-04-14 14:00:23 -04:00

esaxi_cfg.v

Reorganizing files...too many folders after all.

2015-04-11 00:10:16 -04:00

esaxi.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00

etx_arbiter.v

Fixing startup issues in transmit path:

2015-04-15 16:33:20 -04:00

etx_io.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00

etx_protocol.v

Man that's a lot of yak shaving....

2015-04-13 23:35:21 -04:00

etx.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00