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239ca128c2
-missed connections -mismatched bus widths -missing IP blocks -cleanup -proper DV starts tomorrow
14 lines
135 B
Verilog
14 lines
135 B
Verilog
module BUFIO (/*AUTOARG*/
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// Outputs
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O,
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// Inputs
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I
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);
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input I;
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output O;
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assign O=I;
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endmodule // BUFIO
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