FPGA/oh

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Andreas Olofsson c627827a6b Fifo cleanup

-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules

2015-07-02 16:59:38 -04:00

common

Changing default to simplify instantiation

2015-05-14 22:46:23 -04:00

edma

Making reset sync in emmu

2015-05-23 22:26:15 -04:00

elink

Adding IP packaging script

2015-07-02 16:58:43 -04:00

emailbox

Fifo cleanup

2015-07-02 16:59:38 -04:00

emesh

Fifo cleanup

2015-07-02 16:59:38 -04:00

emmu

Making reset sync in emmu

2015-05-23 22:26:15 -04:00

memory

Fifo cleanup

2015-07-02 16:59:38 -04:00

parallella/package/xilinx

Adding parallella block design

2015-05-22 21:38:39 -04:00

projects/axi_elink

change path

2015-07-02 14:53:21 +02:00

xilibs

Fifo cleanup

2015-07-02 16:59:38 -04:00

.gitignore

Adding register access from RX

2015-04-27 23:51:00 -04:00

CONTRIBUTING.md

Basic infrastructure

2015-04-21 21:36:37 -04:00

COPYING

Basic infrastructure

2015-04-21 21:36:37 -04:00

README.md

Massive commit sequence coming...

2015-04-23 17:48:12 -04:00

README.md

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OH!

Open Hardware (Pure and Simple)

(work in progress...)

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