Andreas Olofsson c627827a6b Fifo cleanup ...

-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules

2015-07-02 16:59:38 -04:00

..

BUFG.v

Cleanup

2015-04-21 21:43:16 -04:00

BUFIO.v

Adding comments

2015-04-23 17:52:46 -04:00

BUFR.v

Cleanup

2015-05-07 23:49:50 -04:00

fifo_async_104x16.v

Fifo cleanup

2015-07-02 16:59:38 -04:00

fifo_async_104x32.v

Fifo cleanup

2015-07-02 16:59:38 -04:00

IBUFDS.v

Adding comments

2015-04-23 17:52:46 -04:00

IBUFGDS.v

Adding comments

2015-04-23 17:52:46 -04:00

IDDR.v

Adding IDDR model

2015-05-15 15:27:45 -04:00

IDELAYCTRL.v

Adding IDELAY elements to xilibs

2015-05-16 22:07:17 -04:00

IDELAYE2.v

Adding IDELAY elements to xilibs

2015-05-16 22:07:17 -04:00

ISERDESE2.v

Adding warning message to ISERDES/OSERDES

2015-05-13 23:33:26 -04:00

MMCME2_ADV.v

Adding warning regarding clock divider

2015-05-15 15:26:59 -04:00

OBUF.v

Adding OBUF model

2015-06-25 15:42:20 -04:00

OBUFDS.v

Comments

2015-04-23 17:52:06 -04:00

OBUFTDS.v

Cleanup

2015-04-21 21:43:16 -04:00

ODDR.v

Fixed ODDR model for SAME_EDGE mode

2015-05-15 09:46:08 -04:00

ODELAYE2.v

Adding PLL and MMCME2 primitives

2015-04-22 13:55:59 -04:00

OSERDESE2.v

Adding warning message to ISERDES/OSERDES

2015-05-13 23:33:26 -04:00

PLLE2_ADV.v

Adding PLLE2_ADV model

2015-05-14 22:49:42 -04:00

PLLE2_BASE.v

Fixing bug in clock frequency parameter

2015-05-07 23:49:07 -04:00

processing_system7.v

Adding a "max" ps7 system for reference

2015-04-22 13:54:52 -04:00

RAM32X1D.v

Cleanup

2015-04-21 21:43:16 -04:00