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60 lines
1.6 KiB
Verilog
60 lines
1.6 KiB
Verilog
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/*###########################################################################
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# Function: Dual port memory wrapper (one read/ one write port)
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# To run without hardware platform dependancy, `define:
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# "TARGET_CLEAN"
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############################################################################
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*/
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module memory_dp(/*AUTOARG*/
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// Outputs
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rd_data,
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// Inputs
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wr_clk, wr_en, wr_addr, wr_data, rd_clk, rd_en, rd_addr
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);
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parameter AW = 14;
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parameter DW = 32;
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parameter WED = DW/8; //one per byte
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parameter MD = 1<<AW;//memory depth
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//write-port
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input wr_clk; //write clock
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input [WED-1:0] wr_en; //write enable vector
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input [AW-1:0] wr_addr;//write address
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input [DW-1:0] wr_data;//write data
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//read-port
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input rd_clk; //read clock
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input rd_en; //read enable
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input [AW-1:0] rd_addr;//read address
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output[DW-1:0] rd_data;//read output data
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//////////////////////
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//SIMPLE MEMORY MODEL
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//////////////////////
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reg [DW-1:0] ram [MD-1:0];
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reg [DW-1:0] rd_data;
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//read port
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always @ (posedge rd_clk)
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if(rd_en)
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rd_data[DW-1:0] <= ram[rd_addr[AW-1:0]];
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//write port
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generate
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genvar i;
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for (i = 0; i < WED; i = i+1) begin: gen_ram
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always @(posedge wr_clk)
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begin
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if (wr_en[i])
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ram[wr_addr[AW-1:0]][(i+1)*8-1:i*8] <= wr_data[(i+1)*8-1:i*8];
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end
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end
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endgenerate
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endmodule // memory_dp
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