mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-17 20:02:53 +08:00
98 lines
3.4 KiB
Tcl
98 lines
3.4 KiB
Tcl
###########################################################
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# Create Managed IP Project
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###########################################################
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create_project -force $design $projdir -part $partname
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set_property target_language Verilog [current_project]
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###########################################################
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# Create filesets and add files to project
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###########################################################
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#HDL
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if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
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#CONSTRAINTS
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if {[string equal [get_filesets -quiet constraints_1] ""]} {
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create_fileset -constrset constraints_1
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}
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if {[llength $constraints_files] != 0} {
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add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files
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}
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#ADDING IP
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if {[llength $ip_files] != 0} {
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add_files -norecurse -fileset [get_filesets sources_1] $ip_files
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}
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foreach file $ip_files {
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#TODO: is this needed?
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set file_obj [get_files -of_objects [get_filesets sources_1] $file]
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set_property "synth_checkpoint_mode" "Singular" $file_obj
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}
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#RERUN/UPGRADE IP
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upgrade_ip [get_ips]
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#TODO: How to check for this status of previous command?
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foreach file $ip_files {
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generate_target all [get_files $file]
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set obj [create_ip_run -force [get_files $file]]
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launch_run -jobs 2 $obj
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wait_on_run $obj
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}
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###########################################################
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# SYNTHESIZE (FOR SANITY)
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###########################################################
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#set_property top $design [current_fileset]
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#launch_runs synth_1 -jobs 2
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#wait_on_run synth_1
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###########################################################
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# Package
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###########################################################
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ipx::package_project -import_files -force -root_dir $projdir
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ipx::remove_memory_map {s_axi} [ipx::current_core]
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ipx::add_memory_map {s_axi} [ipx::current_core]
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ipx::associate_bus_interfaces -busif s_axi -clock sys_clk [ipx::current_core]
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ipx::associate_bus_interfaces -busif m_axi -clock sys_clk [ipx::current_core]
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set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]]
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ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]]
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set_property range {65536} [ipx::get_address_block axi_lite \
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[ipx::get_memory_map s_axi [ipx::current_core]]]
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set_property vendor {www.parallella.org} [ipx::current_core]
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set_property library {user} [ipx::current_core]
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set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
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set_property vendor_display_name {ADAPTEVA} [ipx::current_core]
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set_property company_url {www.parallella.org} [ipx::current_core]
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set_property supported_families { \
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{virtex7} {Production} \
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{qvirtex7} {Production} \
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{kintex7} {Production} \
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{kintex7l} {Production} \
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{qkintex7} {Production} \
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{qkintex7l} {Production} \
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{artix7} {Production} \
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{artix7l} {Production} \
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{aartix7} {Production} \
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{qartix7} {Production} \
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{zynq} {Production} \
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{qzynq} {Production} \
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{azynq} {Production} \
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} [ipx::current_core]
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### Write ZIP archive
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ipx::archive_core [concat $design.zip] [ipx::current_core]
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###########################################################
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# Exit
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###########################################################
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exit
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