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38 lines
579 B
Verilog
38 lines
579 B
Verilog
module pulse2toggle(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in, reset
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);
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//clocks
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input clk;
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input in;
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output out;
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//reset
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input reset; //do we need this???
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reg out;
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wire toggle;
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//if input goes high, toggle output
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//note1: input can only be high for one clock cycle
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//note2: be careful with clock gating
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assign toggle = in ? ~out :
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out;
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always @ (posedge clk or posedge reset)
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if(reset)
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out <= 1'b0;
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else
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out <= toggle;
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endmodule // pulse2toggle
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