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42 lines
825 B
Verilog
42 lines
825 B
Verilog
/*
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#######################################################
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# Synchronizer circuit
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#######################################################
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*/
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module synchronizer (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in, clk, reset
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);
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parameter DW = 1;
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//Input Side
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input [DW-1:0] in;
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input clk;
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input reset;
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//Output Side
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output [DW-1:0] out;
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//Three stages
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reg [DW-1:0] sync_reg0;
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reg [DW-1:0] out;
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//We use two flip-flops for metastability improvement
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always @ (posedge clk or posedge reset)
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if(reset)
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begin
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sync_reg0[DW-1:0] <= {(DW){1'b0}};
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out[DW-1:0] <= {(DW){1'b0}};
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end
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else
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begin
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sync_reg0[DW-1:0] <= in[DW-1:0];
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out[DW-1:0] <= sync_reg0[DW-1:0];
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end
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endmodule // synchronizer
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