FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity
oh/parallella/fpga
History
Andreas Olofsson c84e1c96b7 Adding hdmi pins for parallella
2015-11-09 13:22:08 -05:00
..
headless
Adding hdmi pins for parallella
2015-11-09 13:22:08 -05:00
parallella_base
Moving to active low reset
2015-11-06 16:51:57 -05:00
build_axi_elink.tcl
Massive reorg!
2015-11-06 10:59:22 -05:00
build_parallella_basic.tcl
Massive reorg!
2015-11-06 10:59:22 -05:00
ipi_parallella_elink_base_andreas.tcl
Massive reorg!
2015-11-06 10:59:22 -05:00
ipi_parallella_elink_base_sven.tcl
Massive reorg!
2015-11-06 10:59:22 -05:00
parallella_7020_io.xdc
Fixing typos
2015-11-06 22:40:59 -05:00
parallella_elink_base_bd.tcl
Massive reorg!
2015-11-06 10:59:22 -05:00
parallella_io.xdc
Fixing typos
2015-11-06 22:40:59 -05:00
parallella_timing.xdc
Fixing typos
2015-11-06 22:40:59 -05:00
README.md
Updated system memory map
2015-11-06 20:44:18 -05:00

README.md

P1600: 7010 + 0 GPIO P1601: 7010 + 24 GPIO P1602: 7020 + 48 GPIO A101010: 7010 + 0 GPIO A101020: 7010 + 24 GPIO A101040: 7020 + 48 GPIO

parallella_headless.tcl --product number as argument parallella_display.tcl parallella_sdr.tcl

EDITING SYSTEM>BD IN GUI (ONE TIME..)

  1. create ports
  2. connect wires
  3. run connection automation
  4. create memory map
  5. validate_bd_design
  6. write_bd_tcl ./system_bd.tcl

DESIGN LOOP

  1. Make verilog change..
  2. cd parallella_base; ./build.sh
  3. cd ../headless;; ./build.sh
  4. profit