mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
Andreas Olofsson
c885745f6c
Fixing half/byte zero-out bug
- Interrupted mid coding apparently.. - Upper bits need to be zeroed out for 8/16 bit read responses
=======
OH!
An Open Hardware Library for Chip and FPGA designers written in Verilog
CONTENT
Spec | Description |
---|---|
common | Common utility modules and scripts |
edma | DMA module |
emesh | Epiphany emesh related circuits |
elink | Epiphany point to point LVDS link |
emailbox | Simple mailbox with interrupt output |
emmu | Simple memory transaction translation unit |
memory | Various simple memory structures (RAM/FIFO) |
xilibs | Simulation modules for Xilinx primitives |
LICENSE
The OH! repository source code is licensed under the MIT license unless otherwise specified. See LICENSE for full copyright terms.
CONTRIBUTING
Instructions for contributing can be found HERE.
Languages
Verilog
81.1%
Tcl
10.7%
C
5.6%
Shell
0.8%
Python
0.6%
Other
1.2%