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56 lines
2.2 KiB
Markdown
56 lines
2.2 KiB
Markdown
CODING METHODOLOGY
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## STANDARD
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* Verilog 2005
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## STYLE
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* Max 80 chars per line
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* One input/output statement per line
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* Only single line // comments, no /*..*/
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* Use vector sizes in every statement, ie "assign a[7:0] = myvec[7:0];"
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* Use parameters for reusability and readability
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* Use many short statements in place of one big one
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* Define wires/regs at beginning of file
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* Align input names/comments in column like fashion
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* Avoid redundant begin..end statements
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* Capitalize macros and constants
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* Use lower case for all signal names
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* User upper case for all parameters and constants
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* Use y down to x vectors
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* Use a naming methodology and document it
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* Comment every module port
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* Do not hard code numerical values in body of code
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* Keep parameter names short
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* Use common names: nreset, clk, din, dout, en, rd, wr, addr, etc
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* Make names as short as possible, but not shorter
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* Use _ in constants over 4 bits (eg: 8'h1100_1100)
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## METHODLOGY
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* Use `include files for constants
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* Use `ifndef _CONSTANTS_V to include file only once
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* No timescales in design files (only in testbench)
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* No delay statements in design
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* No logic statements in top level design structures
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* One module per file
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* Prefer parameters in place of global defines
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* Do not use casex
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* Use active low reset
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* Avoid redundant resets
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* Avoid heavily nested if, else statements
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* Don't use defparams, place #(.DW(DW)) in module instantation
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* Always use connection by name (not by order) in module instantiatoin
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* Parametrize as much as possible but not more
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* Place a useful comment every 5-20 lines
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* If you are going to use async reset, use oh_rsync.v
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* Use for loops to reduce bloat and to improve readability
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* If you have to mix clock edges, isolate to discrete modules
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* Use nonblocking (<=) in all sequential statements
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* Use default statements in all case statements
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* Don't use proprietary EDA tool pragmas (use parameters)
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* Only use synthesizable constructs
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* Use $signed() for arithmetic operations on signed types
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* Allowed keywords: assign, always, input, output, wire, reg, module, endmodule, if/else, case, casez, ~,|,&,^,==, >>, <<, >, <,?,posedge, negedge, generate, for(...), begin, end, $signed,
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