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https://github.com/aolofsson/oh.git
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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
243 lines
6.4 KiB
Verilog
243 lines
6.4 KiB
Verilog
`include "etrace_regmap.v"
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module etrace (/*AUTOARG*/
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// Outputs
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data_access_out, data_packet_out, cfg_access_out, cfg_packet_out,
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// Inputs
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trace_clk, trace_trigger, trace_vector, cfg_access_in,
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cfg_packet_in
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);
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parameter VW = 32; //width of vector to sample
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parameter DW = 32; //width of counter
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parameter AW = 32; //width of address input bus
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parameter DEPTH = 1024; //memory depth
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parameter ID = 999;
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parameter NAME = "my";
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parameter RFAW = 6; //
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parameter MW = VW+DW; //memory width should be 64,128,256
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parameter MAW = $clog2(DEPTH);//
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parameter LSB = $clog2(MW/32);//address lsb for memory
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//Logic analyzer interface
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input trace_clk;
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input trace_trigger;
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input [VW-1:0] trace_vector;
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//Data streaming interface
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output data_access_out;
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output [PW-1:0] data_packet_out;
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//Config interface
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input cfg_access_in;
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input [PW-1:0] cfg_packet_in;
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output cfg_access_out;
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output [PW-1:0] cfg_packet_out;
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//local regs
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reg [15:0] cfg_reg;
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reg [DW-1:0] cycle_counter;
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reg [VW-1:0] trace_vector_reg;
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reg [2:0] mi_addr_reg;
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reg [MAW-1:0] trace_addr;
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wire mi_write;
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wire mi_cfg_write;
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wire [MW-1:0] mem_data;
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wire trace_enable_sync;
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wire [3:0] ctrlmode_out;
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wire [DW-1:0] data_out;
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wire [1:0] datamode_out;
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wire [AW-1:0] dstaddr_out;
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wire [AW-1:0] srcaddr_out;
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wire write_out;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [PW-1:0] packet_out; // From e2p of emesh2packet.v
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// End of automatics
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//###########################
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//# PACKET PARSING
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//###########################
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//Config
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packet2emesh p2e0 (/*AUTOINST*/
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// Outputs
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.write_out (write_out),
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.datamode_out (datamode_out[1:0]),
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.ctrlmode_out (ctrlmode_out[3:0]),
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.data_out (data_out[DW-1:0]),
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.dstaddr_out (dstaddr_out[AW-1:0]),
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.srcaddr_out (srcaddr_out[AW-1:0]),
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// Inputs
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.packet_in (packet_in[PW-1:0]));
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//Readback
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emesh2packet e2p0 (/*AUTOINST*/
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// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[3:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.data_in (data_in[DW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]));
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//Data
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emesh2packet e2p0 (/*AUTOINST*/
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// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[3:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.data_in (data_in[DW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]));
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//###########################
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//# REGISTER INTERFACE
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//###########################
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assign mi_write = mi_en & mi_we;
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assign mi_cfg_write = mi_write &
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(mi_addr[31:20] ==ID) &
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(mi_addr[19:16] ==`ETRACE_REGS) &
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(mi_addr[RFAW+1:2]==`ETRACE_CFG);
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assign mi_rd = mi_en &
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(mi_addr[31:20] ==ID) &
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(mi_addr[19:16] ==`ETRACE_MEM);
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//TODO: parametrize
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always @ (posedge mi_clk)
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mi_addr_reg[2:0] <= mi_addr[2:0];
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//TODO: parametrize, keep to 32 bits for now
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assign mi_dout[DW-1:0] = mi_addr_reg[2] ? mem_data[63:32] :
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mem_data[31:0];
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//###########################
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//# CONFIG
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//###########################
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//Destination start address ETRACE_BASEADDR [32 bit]
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//Destination samples ETRACE_SAMPLES [32 bit]
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always @ (posedge mi_clk)
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if(!nreset)
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cfg_reg[15:0] <= 'b0;
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else if (mi_cfg_write)
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cfg_reg[15:0] <= mi_din[15:0];
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assign mi_trace_enable = cfg_reg[0];
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assign mi_loop_enable = cfg_reg[1];//runs forever as circular buffer
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assign mi_async_mode = cfg_reg[2];//treats input signals as async/sync
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assign mi_samplerate = cfg_reg[7:4];
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/*
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* 100MS/s
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* 50MS/s
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* 25MS/s
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* 12.5MS/s
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* 6.25MS/s
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* 3.125Ms/s
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* 1.0Ms/s
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* 0.5Ms/s
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*/
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//###########################
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//# "DMA"
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//###########################
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//With 64 channels + 32 bit timer (==96 bits)
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//Max sample rate??
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//################################
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//# SYNC CFG SIGNALS TO SAMPLE CLK
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//#################################
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dsync #(.DW(1))
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dsync(// Outputs
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.dout (trace_enable),
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// Inputs
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.clk (trace_clk),
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.din (mi_trace_enable)
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);
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//###########################
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//# TIME KEEPER
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//###########################
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//count if trigger enabled and counter enabled (SW + HW)
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always @ (posedge trace_clk)
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if(~trace_enable)
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cycle_counter[DW-1:0] <= 'b0;
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else if (trace_trigger)
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cycle_counter[DW-1:0] <= cycle_counter[DW-1:0] + 1'b1;
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//###########################
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//# SAMPLING LOGIC
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//###########################
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//Change detect logic
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always @ (posedge trace_clk)
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trace_vector_reg[VW-1:0] <= trace_vector[VW-1:0];
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assign change_detect = |(trace_vector_reg[VW-1:0] ^ trace_vector[VW-1:0]);
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//Sample signal
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assign trace_sample = trace_enable &
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trace_trigger &
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change_detect;
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//Address counter
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always @ (posedge trace_clk)
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if(~trace_enable)
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trace_addr[MAW-1:0] <= 'b0;
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else if (trace_sample)
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trace_addr[MAW-1:0] <= trace_addr[MAW-1:0] + 1'b1;
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//Trace memory
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fifo_cdc fifo (// Outputs
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.wait_out (),
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.access_out (access_out),
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.packet_out (packet_out[DW-1:0]),
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// Inputs
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.nreset (nreset),
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.clk_in (clk_in),
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.access_in (access_in),
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.packet_in (packet_in[DW-1:0]),
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.clk_out (clk_out),
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.wait_in (wait_in));
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`ifdef TARGET_SIM
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reg [31:0] ftrace;
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reg [255:0] tracefile;
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initial
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begin
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$sformat(tracefile,"%s%s",NAME,".trace");
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ftrace = $fopen({tracefile}, "w");
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end
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always @ (posedge trace_clk)
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if(trace_sample)
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$fwrite(ftrace, "%h,%0d\n",trace_vector[VW-1:0],cycle_counter[DW-1:0]);
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`endif // `ifdef TARGET_SIM
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endmodule // emailbox
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../memory/hdl" "../../common/hdl")
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// End:
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