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239ca128c2
-missed connections -mismatched bus widths -missing IP blocks -cleanup -proper DV starts tomorrow
314 lines
12 KiB
Verilog
314 lines
12 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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module etx(/*AUTOARG*/
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// Outputs
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ecfg_tx_datain, ecfg_tx_debug, esaxi_emrq_full,
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esaxi_emrq_prog_full, esaxi_emwr_full, esaxi_emwr_prog_full,
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emaxi_emrr_full, emaxi_emrr_prog_full, tx_lclk_p, tx_lclk_n,
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tx_frame_p, tx_frame_n, tx_data_p, tx_data_n,
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// Inputs
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reset, tx_lclk, tx_lclk_out, tx_lclk_par, s_axi_aclk, m_axi_aclk,
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ecfg_tx_clkdiv, ecfg_tx_enable, ecfg_tx_gpio_mode,
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ecfg_tx_mmu_mode, ecfg_dataout, esaxi_emrq_wr_en,
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esaxi_emrq_wr_data, esaxi_emwr_wr_en, esaxi_emwr_wr_data,
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emaxi_emrr_wr_en, emaxi_emrr_wr_data, tx_wr_wait_p, tx_wr_wait_n,
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tx_rd_wait_p, tx_rd_wait_n
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter RFAW = 12;
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//Clocks and reset
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input reset;
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input tx_lclk; //high speed serdes clock
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input tx_lclk_out; //lclk output
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input tx_lclk_par; //slow speed parallel clock
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input s_axi_aclk; //clock for read request and write fifos
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input m_axi_aclk; //clock for read response fifo
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//Configuration signals
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input [3:0] ecfg_tx_clkdiv; //transmit clock divider
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input ecfg_tx_enable; //transmit output buffer enable
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//gpio mode
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input ecfg_tx_gpio_mode; //sets output pins to constant values
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input ecfg_tx_mmu_mode; //sets output pins to constant values
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input [8:0] ecfg_dataout; //data for gpio mode
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output [1:0] ecfg_tx_datain; //{wr_wait,rd_wait}
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//Testing
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output [15:0] ecfg_tx_debug; //various debug signals
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//Read requests (from axi slave)
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input esaxi_emrq_wr_en;
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input [102:0] esaxi_emrq_wr_data;
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output esaxi_emrq_full;
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output esaxi_emrq_prog_full;
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//Write requests (from axi slave)
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input esaxi_emwr_wr_en;
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input [102:0] esaxi_emwr_wr_data;
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output esaxi_emwr_full;
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output esaxi_emwr_prog_full;
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//Read responses (from axi master)
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input emaxi_emrr_wr_en;
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input [102:0] emaxi_emrr_wr_data;
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output emaxi_emrr_full;
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output emaxi_emrr_prog_full;
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//Transmit signals for IO
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output tx_lclk_p; //link clock output (up to 500MHz)
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output tx_lclk_n;
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output tx_frame_p; //transaction frame signal
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output tx_frame_n;
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output [7:0] tx_data_p; //transmit data (dual data rate)
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output [7:0] tx_data_n;
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input tx_wr_wait_p; //incoming pushback on write transactions
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input tx_wr_wait_n;
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input tx_rd_wait_p; //incoming pushback on read transactions
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input tx_rd_wait_n;
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//regs
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reg [15:0] ecfg_tx_debug;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire e_tx_access; // From etx_arbiter of etx_arbiter.v
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wire e_tx_ack; // From etx_protocol of etx_protocol.v
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wire [3:0] e_tx_ctrlmode; // From etx_arbiter of etx_arbiter.v
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wire [31:0] e_tx_data; // From etx_arbiter of etx_arbiter.v
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wire [1:0] e_tx_datamode; // From etx_arbiter of etx_arbiter.v
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wire [31:0] e_tx_dstaddr; // From etx_arbiter of etx_arbiter.v
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wire e_tx_rd_wait; // From etx_protocol of etx_protocol.v
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wire [31:0] e_tx_srcaddr; // From etx_arbiter of etx_arbiter.v
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wire e_tx_wr_wait; // From etx_protocol of etx_protocol.v
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wire e_tx_write; // From etx_arbiter of etx_arbiter.v
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wire emrq_empty; // From s_rq_fifo of fifo_async_103x16.v
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wire [102:0] emrq_rd_data; // From s_rq_fifo of fifo_async_103x16.v
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wire emrq_rd_en; // From etx_arbiter of etx_arbiter.v
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wire emrr_empty; // From m_rr_fifo of fifo_async_103x16.v
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wire [102:0] emrr_rd_data; // From m_rr_fifo of fifo_async_103x16.v
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wire emrr_rd_en; // From etx_arbiter of etx_arbiter.v
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wire emwr_empty; // From s_wr_fifo of fifo_async_103x16.v
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wire [102:0] emwr_rd_data; // From s_wr_fifo of fifo_async_103x16.v
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wire emwr_rd_en; // From etx_arbiter of etx_arbiter.v
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wire [63:0] tx_data_par; // From etx_protocol of etx_protocol.v
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wire [7:0] tx_frame_par; // From etx_protocol of etx_protocol.v
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wire tx_rd_wait; // From etx_io of etx_io.v
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wire tx_wr_wait; // From etx_io of etx_io.v
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// End of automatics
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/************************************************************/
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/*FIFOs */
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/************************************************************/
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/*fifo_async_103x16 AUTO_TEMPLATE (
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// Outputs
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.dout (em@"(substring vl-cell-name 2 4)"_rd_data[102:0]),
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.prog_full (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_prog_full),
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.empty (em@"(substring vl-cell-name 2 4)"_empty),
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.full (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_full),
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//Inputs
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.din (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_wr_data[102:0]),
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.wr_clk (@"(substring vl-cell-name 0 1)"_axi_aclk),
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.wr_en (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_wr_en),
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.rd_clk (tx_lclk_par),
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.rd_en (em@"(substring vl-cell-name 2 4)"_rd_en),
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.rst (reset),
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);
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*/
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//Read request fifo (from slave)
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fifo_async_103x16 s_rq_fifo(/*AUTOINST*/
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// Outputs
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.dout (emrq_rd_data[102:0]), // Templated
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.full (esaxi_emrq_full), // Templated
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.empty (emrq_empty), // Templated
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.prog_full (esaxi_emrq_prog_full), // Templated
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// Inputs
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.rst (reset), // Templated
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.wr_clk (s_axi_aclk), // Templated
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.rd_clk (tx_lclk_par), // Templated
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.din (esaxi_emrq_wr_data[102:0]), // Templated
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.wr_en (esaxi_emrq_wr_en), // Templated
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.rd_en (emrq_rd_en)); // Templated
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//Write fifo (from slave)
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fifo_async_103x16 s_wr_fifo(/*AUTOINST*/
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// Outputs
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.dout (emwr_rd_data[102:0]), // Templated
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.full (esaxi_emwr_full), // Templated
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.empty (emwr_empty), // Templated
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.prog_full (esaxi_emwr_prog_full), // Templated
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// Inputs
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.rst (reset), // Templated
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.wr_clk (s_axi_aclk), // Templated
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.rd_clk (tx_lclk_par), // Templated
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.din (esaxi_emwr_wr_data[102:0]), // Templated
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.wr_en (esaxi_emwr_wr_en), // Templated
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.rd_en (emwr_rd_en)); // Templated
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//Read response fifo (from master)
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fifo_async_103x16 m_rr_fifo(/*AUTOINST*/
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// Outputs
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.dout (emrr_rd_data[102:0]), // Templated
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.full (emaxi_emrr_full), // Templated
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.empty (emrr_empty), // Templated
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.prog_full (emaxi_emrr_prog_full), // Templated
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// Inputs
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.rst (reset), // Templated
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.wr_clk (m_axi_aclk), // Templated
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.rd_clk (tx_lclk_par), // Templated
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.din (emaxi_emrr_wr_data[102:0]), // Templated
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.wr_en (emaxi_emrr_wr_en), // Templated
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.rd_en (emrr_rd_en)); // Templated
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/************************************************************/
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/*ELINK TRANSMIT ARBITER */
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/*-arbiter between write (slave), read request (slave), */
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/* and read response channel (master) */
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/********************1****************************************/
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etx_arbiter etx_arbiter (
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/*AUTOINST*/
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// Outputs
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.emwr_rd_en (emwr_rd_en),
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.emrq_rd_en (emrq_rd_en),
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.emrr_rd_en (emrr_rd_en),
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.e_tx_access (e_tx_access),
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.e_tx_write (e_tx_write),
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.e_tx_datamode (e_tx_datamode[1:0]),
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.e_tx_ctrlmode (e_tx_ctrlmode[3:0]),
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.e_tx_dstaddr (e_tx_dstaddr[31:0]),
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.e_tx_srcaddr (e_tx_srcaddr[31:0]),
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.e_tx_data (e_tx_data[31:0]),
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// Inputs
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.tx_lclk_par (tx_lclk_par),
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.reset (reset),
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.emwr_rd_data (emwr_rd_data[102:0]),
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.emwr_empty (emwr_empty),
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.emrq_rd_data (emrq_rd_data[102:0]),
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.emrq_empty (emrq_empty),
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.emrr_rd_data (emrr_rd_data[102:0]),
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.emrr_empty (emrr_empty),
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.e_tx_rd_wait (e_tx_rd_wait),
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.e_tx_wr_wait (e_tx_wr_wait),
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.e_tx_ack (e_tx_ack));
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/************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/*-translates the 104 bit emesh transaction to elink packeet*/
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/************************************************************/
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etx_protocol etx_protocol (/*AUTOINST*/
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// Outputs
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.e_tx_rd_wait (e_tx_rd_wait),
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.e_tx_wr_wait (e_tx_wr_wait),
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.e_tx_ack (e_tx_ack),
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.tx_frame_par (tx_frame_par[7:0]),
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.tx_data_par (tx_data_par[63:0]),
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.ecfg_tx_datain (ecfg_tx_datain[1:0]),
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// Inputs
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.reset (reset),
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.e_tx_access (e_tx_access),
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.e_tx_write (e_tx_write),
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.e_tx_datamode (e_tx_datamode[1:0]),
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.e_tx_ctrlmode (e_tx_ctrlmode[3:0]),
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.e_tx_dstaddr (e_tx_dstaddr[31:0]),
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.e_tx_srcaddr (e_tx_srcaddr[31:0]),
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.e_tx_data (e_tx_data[31:0]),
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.tx_lclk_par (tx_lclk_par),
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.tx_rd_wait (tx_rd_wait),
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.tx_wr_wait (tx_wr_wait));
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/***********************************************************/
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/*ELINK TRANSMIT I/O LOGIC */
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/*-parallel data and frame as input */
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/*-serializes data for I/O */
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/***********************************************************/
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etx_io etx_io (
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/*AUTOINST*/
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// Outputs
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.tx_lclk_p (tx_lclk_p),
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.tx_lclk_n (tx_lclk_n),
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.tx_frame_p (tx_frame_p),
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.tx_frame_n (tx_frame_n),
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.tx_data_p (tx_data_p[7:0]),
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.tx_data_n (tx_data_n[7:0]),
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.tx_wr_wait (tx_wr_wait),
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.tx_rd_wait (tx_rd_wait),
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// Inputs
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.reset (reset),
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.tx_wr_wait_p (tx_wr_wait_p),
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.tx_wr_wait_n (tx_wr_wait_n),
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.tx_rd_wait_p (tx_rd_wait_p),
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.tx_rd_wait_n (tx_rd_wait_n),
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.tx_lclk_par (tx_lclk_par),
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.tx_lclk (tx_lclk),
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.tx_lclk_out (tx_lclk_out),
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.tx_frame_par (tx_frame_par[7:0]),
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.tx_data_par (tx_data_par[63:0]),
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.ecfg_tx_enable (ecfg_tx_enable),
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.ecfg_tx_gpio_mode (ecfg_tx_gpio_mode),
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.ecfg_tx_clkdiv (ecfg_tx_clkdiv[3:0]),
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.ecfg_dataout (ecfg_dataout[8:0]));
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/************************************************************/
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/*Debug signals */
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/************************************************************/
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always @ (posedge tx_lclk_par)
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begin
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ecfg_tx_debug[15:0] <= {2'b0, //15:14
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e_tx_rd_wait, //13
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e_tx_wr_wait, //12
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emrr_rd_en, //11
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emaxi_emrr_full, //10
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emaxi_emrr_prog_full, //9
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emaxi_emrr_wr_en, //8
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emrq_rd_en, //7
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esaxi_emrq_full, //6
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esaxi_emrq_prog_full, //5
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esaxi_emrq_wr_en, //4
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emwr_rd_en, //3
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esaxi_emwr_full, //2
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esaxi_emwr_prog_full, //1
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esaxi_emwr_wr_en //0
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};
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end
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../stubs/hdl")
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// End:
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