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358 lines
13 KiB
Verilog
358 lines
13 KiB
Verilog
/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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########################################################################
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EPIPHANY CONFIGURATION REGISTER
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########################################################################
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-------------------------------------------------------------
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ESYSRESET ***Elink reset***
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[0] 0 - elink active
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1 - elink in reset
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-------------------------------------------------------------
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ESYSCFGTX ***Elink transmitter configuration***
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[0] 0 - link TX disable
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1 - link TX enable
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[1] 0 - normal pass through transaction mode
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1 - mmu mode
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[3:2] 00 - normal mode
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01 - gpio mode
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10 - auto-increment 64-bit address/data pairs
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11 - reserved
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[7:4] Transmit control mode for eMesh
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[11:8] 0000 - No division, full speed
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0001 - Divide by 2
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Others - Reserved
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-------------------------------------------------------------
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ESYSCFGRX ***Elink receiver configuration***
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[0] 0 - link RX disable
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1 - link RX enable
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[1] 0 - normal transaction mode
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1 - mmu mode
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[3:2] 00 - normal mode
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01 - GPIO mode (drive rd wait pins from registers)
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10 - loopback mode (loops TX-->RX)
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11 - reserved
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[4] 0 - set monitor to count traffic
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1 - set monitor to count congestion
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-------------------------------------------------------------
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ESYSCFGCLK ***Epiphany clock frequency setting***
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[3:0] Output divider
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0000 - Clock turned off
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0001 - CLKIN/64
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0010 - CLKIN/32
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0011 - CLKIN/16
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0100 - CLKIN/8
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0101 - CLKIN/4
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0110 - CLKIN/2
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0111 - CLKIN/1 (full speed)
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1XXX - RESERVED
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[7:4] PLL settings (TBD)
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-------------------------------------------------------------
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ESYSCOREID ***CORE ID***
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[5:0] Column ID-->default at powerup/reset
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[11:6] Row ID
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-------------------------------------------------------------
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ESYSVERSION ***Version number (read only)***
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[7:0] Revision #, incremented in each change (match git?)
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[15:8] Type (features included in FPGA load, same board)
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[23:16] Board platform #
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[31:24] Generation # (needed??)
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-------------------------------------------------------------
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ESYSDATAIN ***Data on elink input pins
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[7:0] rx_data[7:0]
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[8] tx_frame
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[9] tx_wait_rd
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[10] tx_wait_wr
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-------------------------------------------------------------
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ESYSDATAOUT ***Data on eLink output pins
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[7:0] tx_data[7:0]
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[8] tx_frame
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[9] rx_wait_rd
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[10] rx_wait_wr
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-------------------------------------------------------------
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ESYSDEBUG ***Various debug signals from elink
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[31:0] (design specific, generic inferface for now)
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included:
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-all wait signals, (4)
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-fifo fulls,
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-fifo emptys
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-axi access, ready signals for master/slave
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-frame signals (in and out)
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########################################################################
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*/
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// These are WORD addresses (bits 11:2)
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`define E_REG_SYSRESET 10'h010
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`define E_REG_SYSCFGTX 10'h011
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`define E_REG_SYSCFGRX 10'h012
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`define E_REG_SYSCFGCLK 10'h013
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`define E_REG_SYSCOREID 10'h014
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`define E_REG_SYSVERSION 10'h015
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`define E_REG_SYSDATAIN 10'h016
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`define E_REG_SYSDATAOUT 10'h017
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`define E_REG_SYSDEBUG 10'h018
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module ecfg (/*AUTOARG*/
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// Outputs
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mi_dout, ecfg_reset, ecfg_tx_enable, ecfg_tx_mmu_mode,
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ecfg_tx_gpio_mode, ecfg_tx_tp_mode, ecfg_tx_ctrl_mode,
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ecfg_tx_clkdiv, ecfg_rx_enable, ecfg_rx_mmu_mode,
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ecfg_rx_gpio_mode, ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg,
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ecfg_coreid, ecfg_dataout,
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// Inputs
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mi_clk, mi_en, mi_we, mi_addr, mi_din, hw_reset, ecfg_datain,
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ecfg_debug_signals
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);
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//Register file parameters
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/*
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#####################################################################
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COMPILE TIME PARAMETERS
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######################################################################
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*/
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parameter COREID = 12'h808;
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parameter VERSION = 32'h00_00_00_00; // FPGA (gen:plat:type:rev)
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parameter IDW = 12; // Elink ID (row,column coordinate)
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parameter RFAW = 12; // Register file address width
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// NB: The BRAM interface seems to provide BYTE addresses!
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/******************************/
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/*HARDWARE RESET (POR/BUTTON) */
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/******************************/
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input hw_reset;
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/*****************************/
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/*SIMPLE MEMORY INTERFACE */
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/*****************************/
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input mi_clk;
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input mi_en;
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input mi_we; //Single we, must write full words!
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input [RFAW-1:0] mi_addr;
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input [31:0] mi_din;
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output [31:0] mi_dout;
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/*****************************/
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/*ELINK CONTROL SIGNALS */
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/*****************************/
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//RESET
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output ecfg_reset;
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//tx
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output ecfg_tx_enable; //enable signal for TX
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output ecfg_tx_mmu_mode; //enables MMU on transmit path
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output ecfg_tx_gpio_mode; //forces TX output pins to constants
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output ecfg_tx_tp_mode; //auto-generates TX transactions
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output [3:0] ecfg_tx_ctrl_mode; //value for emesh ctrlmode tag
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output [3:0] ecfg_tx_clkdiv; //transmit clock divider
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//rx
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output ecfg_rx_enable; //enable signal for rx
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output ecfg_rx_mmu_mode; //enables MMU on rx path
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output ecfg_rx_gpio_mode; //forces rx wait pins to constants
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//cclk
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output ecfg_cclk_en; //cclk enable
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output [3:0] ecfg_cclk_div; //cclk divider setting
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output [3:0] ecfg_cclk_pllcfg; //pll configuration
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//coreid
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output [11:0] ecfg_coreid; //core-id of fpga elink
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//gpio
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input [10:0] ecfg_datain; // data from elink inputs
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output [10:0] ecfg_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0]}
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//debug
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input [31:0] ecfg_debug_signals;//various signals for debugging the elink hardware
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/*------------------------BODY CODE---------------------------------------*/
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//registers
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reg [11:0] ecfg_cfgtx_reg;
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reg [4:0] ecfg_cfgrx_reg;
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reg [7:0] ecfg_cfgclk_reg;
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reg [11:0] ecfg_coreid_reg;
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reg ecfg_reset_reg;
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reg [11:0] ecfg_datain_reg;
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reg [11:0] ecfg_dataout_reg;
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reg [31:0] mi_dout;
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//wires
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wire ecfg_read;
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wire ecfg_write;
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wire ecfg_reset_match;
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wire ecfg_cfgtx_match;
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wire ecfg_cfgrx_match;
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wire ecfg_cfgclk_match;
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wire ecfg_coreid_match;
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wire ecfg_datain_match;
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wire ecfg_dataout_match;
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wire ecfg_match;
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wire ecfg_regmux;
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wire [31:0] ecfg_reg_mux;
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wire ecfg_cfgtx_write;
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wire ecfg_cfgrx_write;
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wire ecfg_cfgclk_write;
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wire ecfg_coreid_write;
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wire ecfg_dataout_write;
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wire ecfg_rx_monitor_mode;
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wire ecfg_reset_write;
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/*****************************/
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/*ADDRESS DECODE LOGIC */
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/*****************************/
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//read/write decode
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assign ecfg_write = mi_en & mi_we;
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assign ecfg_read = mi_en & ~mi_we;
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//address match signals
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assign ecfg_reset_match = mi_addr[RFAW-1:2]==`E_REG_SYSRESET;
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assign ecfg_cfgtx_match = mi_addr[RFAW-1:2]==`E_REG_SYSCFGTX;
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assign ecfg_cfgrx_match = mi_addr[RFAW-1:2]==`E_REG_SYSCFGRX;
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assign ecfg_cfgclk_match = mi_addr[RFAW-1:2]==`E_REG_SYSCFGCLK;
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assign ecfg_coreid_match = mi_addr[RFAW-1:2]==`E_REG_SYSCOREID;
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assign ecfg_version_match = mi_addr[RFAW-1:2]==`E_REG_SYSVERSION;
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assign ecfg_datain_match = mi_addr[RFAW-1:2]==`E_REG_SYSDATAIN;
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assign ecfg_dataout_match = mi_addr[RFAW-1:2]==`E_REG_SYSDATAOUT;
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assign ecfg_match = ecfg_reset_match |
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ecfg_cfgtx_match |
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ecfg_cfgrx_match |
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ecfg_cfgclk_match |
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ecfg_coreid_match |
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ecfg_version_match |
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ecfg_datain_match |
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ecfg_dataout_match;
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//Write enables
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assign ecfg_reset_write = ecfg_reset_match & ecfg_write;
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assign ecfg_cfgtx_write = ecfg_cfgtx_match & ecfg_write;
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assign ecfg_cfgrx_write = ecfg_cfgrx_match & ecfg_write;
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assign ecfg_cfgclk_write = ecfg_cfgclk_match & ecfg_write;
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assign ecfg_coreid_write = ecfg_coreid_match & ecfg_write;
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assign ecfg_dataout_write = ecfg_dataout_match & ecfg_write;
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//###########################
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//# ESYSCFGTX
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//###########################
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always @ (posedge mi_clk)
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if(hw_reset)
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ecfg_cfgtx_reg[11:0] <= 12'b0;
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else if (ecfg_cfgtx_write)
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ecfg_cfgtx_reg[11:0] <= mi_din[11:0];
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assign ecfg_tx_enable = ecfg_cfgtx_reg[0];
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assign ecfg_tx_mmu_mode = ecfg_cfgtx_reg[1];
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assign ecfg_tx_gpio_mode = ecfg_cfgtx_reg[3:2]==2'b01;
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assign ecfg_tx_tp_mode = ecfg_cfgtx_reg[3:2]==2'b10;
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assign ecfg_tx_ctrl_mode[3:0] = ecfg_cfgtx_reg[7:4];
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assign ecfg_tx_clkdiv[3:0] = ecfg_cfgtx_reg[11:8];
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//###########################
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//# ESYSCFGRX
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//###########################
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always @ (posedge mi_clk)
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if(hw_reset)
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ecfg_cfgrx_reg[4:0] <= 5'b0;
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else if (ecfg_cfgrx_write)
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ecfg_cfgrx_reg[4:0] <= mi_din[4:0];
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assign ecfg_rx_enable = ecfg_cfgrx_reg[0];
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assign ecfg_rx_mmu_mode = ecfg_cfgrx_reg[1];
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assign ecfg_rx_gpio_mode = ecfg_cfgrx_reg[3:2]==2'b01;
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assign ecfg_rx_loopback_mode = ecfg_cfgrx_reg[3:2]==2'b10;
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assign ecfg_rx_monitor_mode = ecfg_cfgrx_reg[4];
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//###########################
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//# ESYSCFGCLK
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//###########################
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always @ (posedge mi_clk)
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if(hw_reset)
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ecfg_cfgclk_reg[7:0] <= 8'b0;
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else if (ecfg_cfgclk_write)
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ecfg_cfgclk_reg[7:0] <= mi_din[7:0];
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assign ecfg_cclk_en = ~(ecfg_cfgclk_reg[3:0]==4'b0000);
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assign ecfg_cclk_div[3:0] = ecfg_cfgclk_reg[3:0];
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assign ecfg_cclk_pllcfg[3:0] = ecfg_cfgclk_reg[7:4];
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//###########################
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//# ESYSCOREID
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//###########################
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always @ (posedge mi_clk)
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if(hw_reset)
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ecfg_coreid_reg[IDW-1:0] <= PARAM_COREID;
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else if (ecfg_coreid_write)
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ecfg_coreid_reg[IDW-1:0] <= mi_din[IDW-1:0];
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assign ecfg_coreid[IDW-1:0] = ecfg_coreid_reg[IDW-1:0];
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//###########################
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//# ESYSDATAIN
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//###########################
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always @ (posedge mi_clk)
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ecfg_datain_reg <= ecfg_datain;
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//###########################
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//# ESYSDATAOUT
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//###########################
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always @ (posedge mi_clk)
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if(hw_reset)
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ecfg_dataout_reg <= 'd0;
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else if (ecfg_dataout_write)
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ecfg_dataout_reg <= mi_din[10:0];
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assign ecfg_dataout[10:0] = ecfg_dataout_reg[10:0];
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//###########################
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//# ESYSRESET
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//###########################
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always @ (posedge mi_clk)
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if(hw_reset)
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ecfg_reset_reg <= 1'b0;
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else if (ecfg_reset_write)
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ecfg_reset_reg <= mi_din[0];
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assign ecfg_reset = ecfg_reset_reg | hw_reset;
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//###############################
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//# DATA READBACK MUX
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//###############################
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//Pipelineing readback
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always @ (posedge mi_clk)
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if(ecfg_read)
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case(mi_addr[RFAW-1:2])
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`E_REG_SYSRESET: mi_dout[31:0] <= {31'b0, ecfg_reset_reg};
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`E_REG_SYSCFGTX: mi_dout[31:0] <= {20'b0, ecfg_cfgtx_reg[11:0]};
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`E_REG_SYSCFGRX: mi_dout[31:0] <= {27'b0, ecfg_cfgrx_reg[4:0]};
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`E_REG_SYSCFGCLK: mi_dout[31:0] <= {24'b0, ecfg_cfgclk_reg[7:0]};
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`E_REG_SYSCOREID: mi_dout[31:0] <= {{(32-IDW){1'b0}}, ecfg_coreid_reg[IDW-1:0]};
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`E_REG_SYSVERSION: mi_dout[31:0] <= VERSION;
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`E_REG_SYSDATAIN: mi_dout[31:0] <= {20'b0, ecfg_datain_reg[11:0]};
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`E_REG_SYSDATAOUT: mi_dout[31:0] <= {20'b0, ecfg_dataout_reg[11:0]};
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`E_REG_SYSDEBUG: mi_dout[31:0] <= ecfg_debug_signals[31:0];
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default: mi_dout[31:0] <= 32'd0;
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endcase
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endmodule // e_cfg
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