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655 lines
26 KiB
Verilog
655 lines
26 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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module e_link(/*AUTOARG*/
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// Outputs
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rowid, colid, reset_n, cclk_p, cclk_n, rx_wr_wait_p, rx_wr_wait_n,
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rx_rd_wait_p, rx_rd_wait_n, tx_lclk_p, tx_lclk_n, tx_frame_p,
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tx_frame_n, tx_data_p, tx_data_n, embox_not_empty, embox_full,
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m_axi_araddr, m_axi_arburst, m_axi_arcache, m_axi_arid,
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m_axi_arlen, m_axi_arlock, m_axi_arprot, m_axi_arqos, m_axi_arsize,
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m_axi_arvalid, m_axi_awaddr, m_axi_awburst, m_axi_awcache,
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m_axi_awid, m_axi_awlen, m_axi_awlock, m_axi_awprot, m_axi_awqos,
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m_axi_awsize, m_axi_awvalid, m_axi_bready, m_axi_rready,
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m_axi_wdata, m_axi_wlast, m_axi_wstrb, m_axi_wvalid, s_axi_arready,
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s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rdata,
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s_axi_rid, s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready,
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s_axicfg_arready, s_axicfg_awready, s_axicfg_bresp,
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s_axicfg_bvalid, s_axicfg_rdata, s_axicfg_rresp, s_axicfg_rvalid,
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s_axicfg_wready,
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// Inputs
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hw_reset, clkin, rx_lclk_p, rx_lclk_n, rx_frame_p, rx_frame_n,
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rx_data_p, rx_data_n, tx_wr_wait_p, tx_wr_wait_n, tx_rd_wait_p,
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tx_rd_wait_n, m_axi_aclk, m_axi_aresetn, m_axi_arready,
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m_axi_awready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_rdata,
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m_axi_rid, m_axi_rlast, m_axi_rresp, m_axi_rvalid, m_axi_wready,
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s_axi_aclk, s_axi_aresetn, s_axi_araddr, s_axi_arburst,
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s_axi_arcache, s_axi_arid, s_axi_arlen, s_axi_arlock, s_axi_arprot,
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s_axi_arqos, s_axi_arregion, s_axi_arsize, s_axi_arvalid,
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s_axi_awaddr, s_axi_awburst, s_axi_awcache, s_axi_awid,
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s_axi_awlen, s_axi_awlock, s_axi_awprot, s_axi_awqos,
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s_axi_awregion, s_axi_awsize, s_axi_awvalid, s_axi_bready,
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s_axi_rready, s_axi_wdata, s_axi_wlast, s_axi_wstrb, s_axi_wvalid,
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s_axicfg_araddr, s_axicfg_arprot, s_axicfg_arvalid,
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s_axicfg_awaddr, s_axicfg_awprot, s_axicfg_awvalid,
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s_axicfg_bready, s_axicfg_rready, s_axicfg_wdata, s_axicfg_wstrb,
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s_axicfg_wvalid
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);
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parameter COREID = `CFG_COREID;
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/****************************/
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/*BASIC SIGNALS */
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/****************************/
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input hw_reset; //active high asynchronous hardware reset
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input clkin; //primary clock input
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/*****************************/
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/*EPIPHANY BASIC INTERFACE */
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/*****************************/
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output [3:0] rowid; //row id to drive out to Epiphany
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output [3:0] colid; //col id to drive out to Epiphany
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output reset_n; //reset signal for Epiphany (active low)
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output cclk_p; //high speed core clock (1GHz) to Epiphany
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output cclk_n;
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/*****************************/
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/*ELINK INTERFACE (I/O PINS) */
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/*****************************/
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//Receiver
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input rx_lclk_p; //linkh speed clock input (up to 500MHz)
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input rx_lclk_n;
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input rx_frame_p; //transaction frame signal
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input rx_frame_n;
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input [7:0] rx_data_p; //receive data (dual data rate)
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input [7:0] rx_data_n;
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output rx_wr_wait_p; //outgoing pushback on write transactions
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output rx_wr_wait_n;
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output rx_rd_wait_p; //outgoing pushback on read transactions
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output rx_rd_wait_n;
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//Transmitter
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output tx_lclk_p; //hlink clock output (up to 500MHz)
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output tx_lclk_n;
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output tx_frame_p; //transaction frame signal
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output tx_frame_n;
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output [7:0] tx_data_p; //transmit data (dual data rate)
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output [7:0] tx_data_n;
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input tx_wr_wait_p; //incoming pushback on write transactions
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input tx_wr_wait_n;
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input tx_rd_wait_p; //incoming pushback on read transactions
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input tx_rd_wait_n;
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/*****************************/
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/*MAILBOX */
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/*****************************/
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output embox_not_empty;
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output embox_full;
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/*****************************/
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/*AXI master interface */
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/*****************************/
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//Clock and reset
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input m_axi_aclk;
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input m_axi_aresetn;
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//Read address channel
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output [31:0] m_axi_araddr; //read address
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output [1:0] m_axi_arburst; //burst type
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output [3:0] m_axi_arcache; //memory type
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output [0:0] m_axi_arid; //address ID
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output [7:0] m_axi_arlen; //burst length (number of data transfers)
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output [0:0] m_axi_arlock; //lock type (atomic characteristics)
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output [2:0] m_axi_arprot; //protection type
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output [3:0] m_axi_arqos; //quality of service (setting?)
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input m_axi_arready; //read ready
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output [2:0] m_axi_arsize; //burst size (the size of each transfer)
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output m_axi_arvalid; //write address valid
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//Write address channel
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output [31:0] m_axi_awaddr;
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output [1:0] m_axi_awburst;
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output [3:0] m_axi_awcache;
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output [0:0] m_axi_awid;
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output [7:0] m_axi_awlen;
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output [0:0] m_axi_awlock;
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output [2:0] m_axi_awprot;
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output [3:0] m_axi_awqos;
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input m_axi_awready;
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output [2:0] m_axi_awsize;
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output m_axi_awvalid;
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//Buffered write response channel
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input [0:0] m_axi_bid; //response tag
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output m_axi_bready;
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input [1:0] m_axi_bresp;
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input m_axi_bvalid;
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//Read channel
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input [63:0] m_axi_rdata;
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input [0:0] m_axi_rid; //read id tag
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input m_axi_rlast; //indicates last transfer of a burst
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output m_axi_rready; //read ready signal
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input [1:0] m_axi_rresp;
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input m_axi_rvalid;
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//Write channel
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output [63:0] m_axi_wdata;
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output m_axi_wlast; //indicates last transfer of a burs
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input m_axi_wready; //response ready
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output [7:0] m_axi_wstrb;
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output m_axi_wvalid;
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/*****************************/
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/*AXI slave interface */
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/*****************************/
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//Clock and reset
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input s_axi_aclk;
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input s_axi_aresetn;
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//Read address channel
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input [29:0] s_axi_araddr;
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input [1:0] s_axi_arburst;
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input [3:0] s_axi_arcache;
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input [11:0] s_axi_arid;
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input [7:0] s_axi_arlen;
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input [0:0] s_axi_arlock;
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input [2:0] s_axi_arprot;
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input [3:0] s_axi_arqos;
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output s_axi_arready;
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input [3:0] s_axi_arregion;
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input [2:0] s_axi_arsize;
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input s_axi_arvalid;
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//Write address channel
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input [29:0] s_axi_awaddr;
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input [1:0] s_axi_awburst;
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input [3:0] s_axi_awcache;
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input [11:0] s_axi_awid;
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input [7:0] s_axi_awlen;
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input [0:0] s_axi_awlock;
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input [2:0] s_axi_awprot;
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input [3:0] s_axi_awqos;
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output s_axi_awready;
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input [3:0] s_axi_awregion;
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input [2:0] s_axi_awsize;
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input s_axi_awvalid;
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//Buffered write response channel
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output [11:0] s_axi_bid;
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input s_axi_bready;
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output [1:0] s_axi_bresp;
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output s_axi_bvalid;
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//Read channel
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output [31:0] s_axi_rdata;
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output [11:0] s_axi_rid;
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output s_axi_rlast;
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input s_axi_rready;
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output [1:0] s_axi_rresp;
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output s_axi_rvalid;
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//Write channel
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input [31:0] s_axi_wdata;
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input s_axi_wlast;
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output s_axi_wready;
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input [3:0] s_axi_wstrb;
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input s_axi_wvalid;
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/*****************************/
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/*AXI config slave interface */
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/*****************************/
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//read address channel
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input [12:0] s_axicfg_araddr;
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input [2:0] s_axicfg_arprot;
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output s_axicfg_arready;
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input s_axicfg_arvalid;
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//write address channel
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input [12:0] s_axicfg_awaddr;
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input [2:0] s_axicfg_awprot;
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output s_axicfg_awready;
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input s_axicfg_awvalid;
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//buffered read response channel
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input s_axicfg_bready;
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output [1:0] s_axicfg_bresp;
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output s_axicfg_bvalid;
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//read channel
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output [31:0] s_axicfg_rdata;
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input s_axicfg_rready;
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output [1:0] s_axicfg_rresp;
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output s_axicfg_rvalid;
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//write channel
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input [31:0] s_axicfg_wdata;
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output s_axicfg_wready;
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input [3:0] s_axicfg_wstrb;
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input s_axicfg_wvalid;
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//wires
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wire [31:0] mi_rd_data;
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wire [31:0] mi_dout_ecfg;
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wire [31:0] mi_dout_embox;
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wire [31:0] mi_dout_rx;
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wire [31:0] mi_dout_tx;
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] ecfg_cclk_div; // From ecfg of ecfg.v
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wire ecfg_cclk_en; // From ecfg of ecfg.v
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wire [3:0] ecfg_cclk_pllcfg; // From ecfg of ecfg.v
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wire [11:0] ecfg_coreid; // From ecfg of ecfg.v
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wire [8:0] ecfg_datain; // From erx of erx.v
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wire [10:0] ecfg_dataout; // From ecfg of ecfg.v
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wire [15:0] ecfg_rx_debug_signals; // From erx of erx.v
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wire ecfg_rx_enable; // From ecfg of ecfg.v
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wire ecfg_rx_gpio_mode; // From ecfg of ecfg.v
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wire ecfg_rx_mmu_mode; // From ecfg of ecfg.v
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wire [3:0] ecfg_tx_clkdiv; // From ecfg of ecfg.v
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wire [3:0] ecfg_tx_ctrl_mode; // From ecfg of ecfg.v
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wire [15:0] ecfg_tx_debug_signals; // From etx of etx.v
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wire ecfg_tx_enable; // From ecfg of ecfg.v
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wire ecfg_tx_gpio_mode; // From ecfg of ecfg.v
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wire ecfg_tx_mmu_mode; // From ecfg of ecfg.v
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wire ecfg_tx_tp_mode; // From ecfg of ecfg.v
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wire emaxi_emrq_empty; // From erx of erx.v
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wire [102:0] emaxi_emrq_rd_data; // From erx of erx.v
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wire emaxi_emrq_rd_en; // From emaxi of emaxi.v
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wire emaxi_emrr_full; // From etx of etx.v
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wire emaxi_emrr_prog_full; // From etx of etx.v
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wire [102:0] emaxi_emrr_wr_data; // From emaxi of emaxi.v
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wire emaxi_emrr_wr_en; // From emaxi of emaxi.v
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wire emaxi_emwr_empty; // From erx of erx.v
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wire [102:0] emaxi_emwr_rd_data; // From erx of erx.v
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wire emaxi_emwr_rd_en; // From emaxi of emaxi.v
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wire esaxi_emrq_full; // From etx of etx.v
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wire esaxi_emrq_prog_full; // From etx of etx.v
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wire [102:0] esaxi_emrq_wr_data; // From esaxi of esaxi.v
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wire esaxi_emrq_wr_en; // From esaxi of esaxi.v
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wire esaxi_emrr_empty; // From erx of erx.v
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wire [102:0] esaxi_emrr_rd_data; // From erx of erx.v
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wire esaxi_emrr_rd_en; // From esaxi of esaxi.v
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wire esaxi_emwr_full; // From etx of etx.v
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wire esaxi_emwr_prog_full; // From etx of etx.v
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wire [102:0] esaxi_emwr_wr_data; // From esaxi of esaxi.v
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wire esaxi_emwr_wr_en; // From esaxi of esaxi.v
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wire [RFAW-1:0] mi_addr; // From esaxilite of esaxilite.v
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wire mi_clk; // From esaxilite of esaxilite.v
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wire [31:0] mi_din; // From esaxilite of esaxilite.v
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wire mi_en; // From esaxilite of esaxilite.v
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wire mi_we; // From esaxilite of esaxilite.v
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wire reset; // From ecfg of ecfg.v
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wire txlclk_out; // From eclock of eclock.v
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wire txlclk_p; // From eclock of eclock.v
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wire txlclk_s; // From eclock of eclock.v
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// End of automatics
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/***********************************************************/
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/*AXI MASTER */
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/***********************************************************/
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/*emaxi AUTO_TEMPLATE (
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// Outputs
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.m00_\(.*\) (m_\1[]),
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.em\(.*\) (emaxi_em\1[]),
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);
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*/
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emaxi emaxi(/*AUTOINST*/
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// Outputs
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.emwr_rd_en (emaxi_emwr_rd_en), // Templated
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.emrq_rd_en (emaxi_emrq_rd_en), // Templated
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.emrr_wr_data (emaxi_emrr_wr_data[102:0]), // Templated
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.emrr_wr_en (emaxi_emrr_wr_en), // Templated
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.m00_axi_awid (m_axi_awid[0:0]), // Templated
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.m00_axi_awaddr (m_axi_awaddr[31:0]), // Templated
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.m00_axi_awlen (m_axi_awlen[7:0]), // Templated
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.m00_axi_awsize (m_axi_awsize[2:0]), // Templated
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.m00_axi_awburst (m_axi_awburst[1:0]), // Templated
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.m00_axi_awlock (m_axi_awlock), // Templated
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.m00_axi_awcache (m_axi_awcache[3:0]), // Templated
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.m00_axi_awprot (m_axi_awprot[2:0]), // Templated
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.m00_axi_awqos (m_axi_awqos[3:0]), // Templated
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.m00_axi_awvalid (m_axi_awvalid), // Templated
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.m00_axi_wdata (m_axi_wdata[31:0]), // Templated
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.m00_axi_wstrb (m_axi_wstrb[3:0]), // Templated
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.m00_axi_wlast (m_axi_wlast), // Templated
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.m00_axi_wvalid (m_axi_wvalid), // Templated
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.m00_axi_bready (m_axi_bready), // Templated
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.m00_axi_arid (m_axi_arid[0:0]), // Templated
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.m00_axi_araddr (m_axi_araddr[31:0]), // Templated
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.m00_axi_arlen (m_axi_arlen[7:0]), // Templated
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.m00_axi_arsize (m_axi_arsize[2:0]), // Templated
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.m00_axi_arburst (m_axi_arburst[1:0]), // Templated
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.m00_axi_arlock (m_axi_arlock), // Templated
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.m00_axi_arcache (m_axi_arcache[3:0]), // Templated
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.m00_axi_arprot (m_axi_arprot[2:0]), // Templated
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.m00_axi_arqos (m_axi_arqos[3:0]), // Templated
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.m00_axi_arvalid (m_axi_arvalid), // Templated
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.m00_axi_rready (m_axi_rready), // Templated
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// Inputs
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.emwr_rd_data (emaxi_emwr_rd_data[102:0]), // Templated
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.emwr_empty (emaxi_emwr_empty), // Templated
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.emrq_rd_data (emaxi_emrq_rd_data[102:0]), // Templated
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.emrq_empty (emaxi_emrq_empty), // Templated
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.emrr_full (emaxi_emrr_full), // Templated
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.emrr_prog_full (emaxi_emrr_prog_full), // Templated
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.m00_axi_aclk (m_axi_aclk), // Templated
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.m00_axi_aresetn (m_axi_aresetn), // Templated
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.m00_axi_awready (m_axi_awready), // Templated
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.m00_axi_wready (m_axi_wready), // Templated
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.m00_axi_bid (m_axi_bid[0:0]), // Templated
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.m00_axi_bresp (m_axi_bresp[1:0]), // Templated
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.m00_axi_bvalid (m_axi_bvalid), // Templated
|
|
.m00_axi_arready (m_axi_arready), // Templated
|
|
.m00_axi_rid (m_axi_rid[0:0]), // Templated
|
|
.m00_axi_rdata (m_axi_rdata[31:0]), // Templated
|
|
.m00_axi_rresp (m_axi_rresp[1:0]), // Templated
|
|
.m00_axi_rlast (m_axi_rlast), // Templated
|
|
.m00_axi_rvalid (m_axi_rvalid)); // Templated
|
|
|
|
/***********************************************************/
|
|
/*AXI SLAVE */
|
|
/***********************************************************/
|
|
/*esaxi AUTO_TEMPLATE (
|
|
// Outputs
|
|
.s00_\(.*\) (s_\1[]),
|
|
.em\(.*\) (esaxi_em\1[]),
|
|
);
|
|
*/
|
|
|
|
esaxi esaxi(/*AUTOINST*/
|
|
// Outputs
|
|
.emwr_wr_data (esaxi_emwr_wr_data[102:0]), // Templated
|
|
.emwr_wr_en (esaxi_emwr_wr_en), // Templated
|
|
.emrq_wr_data (esaxi_emrq_wr_data[102:0]), // Templated
|
|
.emrq_wr_en (esaxi_emrq_wr_en), // Templated
|
|
.emrr_rd_en (esaxi_emrr_rd_en), // Templated
|
|
.s00_axi_awready (s_axi_awready), // Templated
|
|
.s00_axi_wready (s_axi_wready), // Templated
|
|
.s00_axi_bid (s_axi_bid[0:0]), // Templated
|
|
.s00_axi_bresp (s_axi_bresp[1:0]), // Templated
|
|
.s00_axi_bvalid (s_axi_bvalid), // Templated
|
|
.s00_axi_arready (s_axi_arready), // Templated
|
|
.s00_axi_rid (s_axi_rid[0:0]), // Templated
|
|
.s00_axi_rdata (s_axi_rdata[31:0]), // Templated
|
|
.s00_axi_rresp (s_axi_rresp[1:0]), // Templated
|
|
.s00_axi_rlast (s_axi_rlast), // Templated
|
|
.s00_axi_rvalid (s_axi_rvalid), // Templated
|
|
// Inputs
|
|
.emwr_full (esaxi_emwr_full), // Templated
|
|
.emwr_prog_full (esaxi_emwr_prog_full), // Templated
|
|
.emrq_full (esaxi_emrq_full), // Templated
|
|
.emrq_prog_full (esaxi_emrq_prog_full), // Templated
|
|
.emrr_rd_data (esaxi_emrr_rd_data[102:0]), // Templated
|
|
.emrr_empty (esaxi_emrr_empty), // Templated
|
|
.ecfg_tx_ctrl_mode (ecfg_tx_ctrl_mode[3:0]),
|
|
.ecfg_coreid (ecfg_coreid[11:0]),
|
|
.s00_axi_aclk (s_axi_aclk), // Templated
|
|
.s00_axi_aresetn (s_axi_aresetn), // Templated
|
|
.s00_axi_awid (s_axi_awid[0:0]), // Templated
|
|
.s00_axi_awaddr (s_axi_awaddr[29:0]), // Templated
|
|
.s00_axi_awlen (s_axi_awlen[7:0]), // Templated
|
|
.s00_axi_awsize (s_axi_awsize[2:0]), // Templated
|
|
.s00_axi_awburst (s_axi_awburst[1:0]), // Templated
|
|
.s00_axi_awlock (s_axi_awlock), // Templated
|
|
.s00_axi_awcache (s_axi_awcache[3:0]), // Templated
|
|
.s00_axi_awprot (s_axi_awprot[2:0]), // Templated
|
|
.s00_axi_awqos (s_axi_awqos[3:0]), // Templated
|
|
.s00_axi_awregion (s_axi_awregion[3:0]), // Templated
|
|
.s00_axi_awvalid (s_axi_awvalid), // Templated
|
|
.s00_axi_wdata (s_axi_wdata[31:0]), // Templated
|
|
.s00_axi_wstrb (s_axi_wstrb[3:0]), // Templated
|
|
.s00_axi_wlast (s_axi_wlast), // Templated
|
|
.s00_axi_wvalid (s_axi_wvalid), // Templated
|
|
.s00_axi_bready (s_axi_bready), // Templated
|
|
.s00_axi_arid (s_axi_arid[0:0]), // Templated
|
|
.s00_axi_araddr (s_axi_araddr[29:0]), // Templated
|
|
.s00_axi_arlen (s_axi_arlen[7:0]), // Templated
|
|
.s00_axi_arsize (s_axi_arsize[2:0]), // Templated
|
|
.s00_axi_arburst (s_axi_arburst[1:0]), // Templated
|
|
.s00_axi_arlock (s_axi_arlock), // Templated
|
|
.s00_axi_arcache (s_axi_arcache[3:0]), // Templated
|
|
.s00_axi_arprot (s_axi_arprot[2:0]), // Templated
|
|
.s00_axi_arqos (s_axi_arqos[3:0]), // Templated
|
|
.s00_axi_arregion (s_axi_arregion[3:0]), // Templated
|
|
.s00_axi_arvalid (s_axi_arvalid), // Templated
|
|
.s00_axi_rready (s_axi_rready)); // Templated
|
|
|
|
/***********************************************************/
|
|
/*AXI CONFIGURATION SLAVE (LITE) */
|
|
/***********************************************************/
|
|
|
|
esaxilite esaxilite(
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.s_axicfg_arready(s_axicfg_arready),
|
|
.s_axicfg_awready(s_axicfg_awready),
|
|
.s_axicfg_bresp (s_axicfg_bresp[1:0]),
|
|
.s_axicfg_bvalid(s_axicfg_bvalid),
|
|
.s_axicfg_rdata (s_axicfg_rdata[31:0]),
|
|
.s_axicfg_rresp (s_axicfg_rresp[1:0]),
|
|
.s_axicfg_rvalid(s_axicfg_rvalid),
|
|
.s_axicfg_wready(s_axicfg_wready),
|
|
.mi_clk (mi_clk),
|
|
.mi_en (mi_en),
|
|
.mi_we (mi_we),
|
|
.mi_addr (mi_addr[RFAW-1:0]),
|
|
.mi_din (mi_din[31:0]),
|
|
// Inputs
|
|
.s_axicfg_araddr(s_axicfg_araddr[15:0]),
|
|
.s_axicfg_arprot(s_axicfg_arprot[2:0]),
|
|
.s_axicfg_arvalid(s_axicfg_arvalid),
|
|
.s_axicfg_awaddr(s_axicfg_awaddr[15:0]),
|
|
.s_axicfg_awprot(s_axicfg_awprot[2:0]),
|
|
.s_axicfg_awvalid(s_axicfg_awvalid),
|
|
.s_axicfg_bready(s_axicfg_bready),
|
|
.s_axicfg_rready(s_axicfg_rready),
|
|
.s_axicfg_wdata (s_axicfg_wdata[31:0]),
|
|
.s_axicfg_wstrb (s_axicfg_wstrb[3:0]),
|
|
.s_axicfg_wvalid(s_axicfg_wvalid),
|
|
.mi_rd_data (mi_rd_data[31:0]));
|
|
|
|
/***********************************************************/
|
|
/*ELINK CLOCK GENERATOR */
|
|
/***********************************************************/
|
|
|
|
eclock eclock(/*AUTOINST*/
|
|
// Outputs
|
|
.cclk_p (cclk_p),
|
|
.cclk_n (cclk_n),
|
|
.txlclk_s (txlclk_s),
|
|
.txlclk_out (txlclk_out),
|
|
.txlclk_p (txlclk_p),
|
|
// Inputs
|
|
.clkin (clkin),
|
|
.reset (reset),
|
|
.ecfg_cclk_en (ecfg_cclk_en),
|
|
.ecfg_cclk_div (ecfg_cclk_div[3:0]),
|
|
.ecfg_cclk_pllcfg (ecfg_cclk_pllcfg[3:0]));
|
|
|
|
|
|
/***********************************************************/
|
|
/*RECEIVER */
|
|
/***********************************************************/
|
|
|
|
erx erx(.mi_dout (mi_dout_rx[DW-1:0]),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.ecfg_rx_debug_signals (ecfg_rx_debug_signals[15:0]),
|
|
.ecfg_datain (ecfg_datain[8:0]),
|
|
.emaxi_emwr_empty (emaxi_emwr_empty),
|
|
.emaxi_emwr_rd_data (emaxi_emwr_rd_data[102:0]),
|
|
.emaxi_emrq_empty (emaxi_emrq_empty),
|
|
.emaxi_emrq_rd_data (emaxi_emrq_rd_data[102:0]),
|
|
.esaxi_emrr_empty (esaxi_emrr_empty),
|
|
.esaxi_emrr_rd_data (esaxi_emrr_rd_data[102:0]),
|
|
.rx_wr_wait_p (rx_wr_wait_p),
|
|
.rx_wr_wait_n (rx_wr_wait_n),
|
|
.rx_rd_wait_p (rx_rd_wait_p),
|
|
.rx_rd_wait_n (rx_rd_wait_n),
|
|
// Inputs
|
|
.reset (reset),
|
|
.s_axi_aclk (s_axi_aclk),
|
|
.m_axi_aclk (m_axi_aclk),
|
|
.ecfg_rx_enable (ecfg_rx_enable),
|
|
.ecfg_rx_mmu_mode (ecfg_rx_mmu_mode),
|
|
.ecfg_rx_gpio_mode (ecfg_rx_gpio_mode),
|
|
.ecfg_dataout (ecfg_dataout[10:0]),
|
|
.emaxi_emwr_rd_en (emaxi_emwr_rd_en),
|
|
.emaxi_emrq_rd_en (emaxi_emrq_rd_en),
|
|
.esaxi_emrr_rd_en (esaxi_emrr_rd_en),
|
|
.rx_lclk_p (rx_lclk_p),
|
|
.rx_lclk_n (rx_lclk_n),
|
|
.rx_frame_p (rx_frame_p),
|
|
.rx_frame_n (rx_frame_n),
|
|
.rx_data_p (rx_data_p[7:0]),
|
|
.rx_data_n (rx_data_n[7:0]),
|
|
.mi_clk (mi_clk),
|
|
.mi_en (mi_en),
|
|
.mi_we (mi_we),
|
|
.mi_addr (mi_addr[RFAW-1:0]),
|
|
.mi_din (mi_din[31:0]));
|
|
|
|
|
|
/***********************************************************/
|
|
/*TRANSMITTER */
|
|
/***********************************************************/
|
|
etx etx(.mi_dout (mi_dout_tx[DW-1:0]),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.ecfg_tx_debug_signals (ecfg_tx_debug_signals[15:0]),
|
|
.esaxi_emrq_full (esaxi_emrq_full),
|
|
.esaxi_emrq_prog_full (esaxi_emrq_prog_full),
|
|
.esaxi_emwr_full (esaxi_emwr_full),
|
|
.esaxi_emwr_prog_full (esaxi_emwr_prog_full),
|
|
.emaxi_emrr_full (emaxi_emrr_full),
|
|
.emaxi_emrr_prog_full (emaxi_emrr_prog_full),
|
|
.tx_lclk_p (tx_lclk_p),
|
|
.tx_lclk_n (tx_lclk_n),
|
|
.tx_frame_p (tx_frame_p),
|
|
.tx_frame_n (tx_frame_n),
|
|
.tx_data_p (tx_data_p[7:0]),
|
|
.tx_data_n (tx_data_n[7:0]),
|
|
// Inputs
|
|
.reset (reset),
|
|
.txlclk_out (txlclk_out),
|
|
.txlclk_p (txlclk_p),
|
|
.txlclk_s (txlclk_s),
|
|
.s_axi_aclk (s_axi_aclk),
|
|
.m_axi_aclk (m_axi_aclk),
|
|
.ecfg_tx_clkdiv (ecfg_tx_clkdiv[3:0]),
|
|
.ecfg_tx_enable (ecfg_tx_enable),
|
|
.ecfg_tx_gpio_mode (ecfg_tx_gpio_mode),
|
|
.ecfg_tx_mmu_mode (ecfg_tx_mmu_mode),
|
|
.ecfg_dataout (ecfg_dataout[10:0]),
|
|
.ecfg_tx_tp_mode (ecfg_tx_tp_mode),
|
|
.esaxi_emrq_wr_en (esaxi_emrq_wr_en),
|
|
.esaxi_emrq_wr_data (esaxi_emrq_wr_data[102:0]),
|
|
.esaxi_emwr_wr_en (esaxi_emwr_wr_en),
|
|
.esaxi_emwr_wr_data (esaxi_emwr_wr_data[102:0]),
|
|
.emaxi_emrr_wr_en (emaxi_emrr_wr_en),
|
|
.emaxi_emrr_wr_data (emaxi_emrr_wr_data[102:0]),
|
|
.tx_wr_wait_p (tx_wr_wait_p),
|
|
.tx_wr_wait_n (tx_wr_wait_n),
|
|
.tx_rd_wait_p (tx_rd_wait_p),
|
|
.tx_rd_wait_n (tx_rd_wait_n));
|
|
|
|
|
|
/***********************************************************/
|
|
/*ELINK CONFIGURATION REGISTERES */
|
|
/***********************************************************/
|
|
|
|
/*ecfg AUTO_TEMPLATE (
|
|
// Outputs
|
|
.ecfg_reset (reset),
|
|
.ecfg_debug_signals ({embox_full, embox_not_empty, ecfg_rx_debug_signals[13:0],ecfg_tx_debug_signals[15:0]}),
|
|
);
|
|
*/
|
|
|
|
|
|
ecfg ecfg(.mi_dout (mi_dout_ecfg[DW-1:0]),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.ecfg_reset (reset), // Templated
|
|
.ecfg_tx_enable (ecfg_tx_enable),
|
|
.ecfg_tx_mmu_mode (ecfg_tx_mmu_mode),
|
|
.ecfg_tx_gpio_mode (ecfg_tx_gpio_mode),
|
|
.ecfg_tx_tp_mode (ecfg_tx_tp_mode),
|
|
.ecfg_tx_ctrl_mode (ecfg_tx_ctrl_mode[3:0]),
|
|
.ecfg_tx_clkdiv (ecfg_tx_clkdiv[3:0]),
|
|
.ecfg_rx_enable (ecfg_rx_enable),
|
|
.ecfg_rx_mmu_mode (ecfg_rx_mmu_mode),
|
|
.ecfg_rx_gpio_mode (ecfg_rx_gpio_mode),
|
|
.ecfg_cclk_en (ecfg_cclk_en),
|
|
.ecfg_cclk_div (ecfg_cclk_div[3:0]),
|
|
.ecfg_cclk_pllcfg (ecfg_cclk_pllcfg[3:0]),
|
|
.ecfg_coreid (ecfg_coreid[11:0]),
|
|
.ecfg_dataout (ecfg_dataout[10:0]),
|
|
// Inputs
|
|
.hw_reset (hw_reset),
|
|
.mi_clk (mi_clk),
|
|
.mi_en (mi_en),
|
|
.mi_we (mi_we),
|
|
.mi_addr (mi_addr[RFAW-1:0]),
|
|
.mi_din (mi_din[31:0]),
|
|
.ecfg_datain (ecfg_datain[10:0]),
|
|
.ecfg_debug_signals ({embox_full, embox_not_empty, ecfg_rx_debug_signals[13:0],ecfg_tx_debug_signals[15:0]})); // Templated
|
|
|
|
|
|
/***********************************************************/
|
|
/*GENERAL PURPOSE MAILBOX */
|
|
/***********************************************************/
|
|
|
|
embox embox(.clk (mi_clk),
|
|
.mi_dout (mi_dout_embox[DW-1:0]),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.embox_full (embox_full),
|
|
.embox_not_empty (embox_not_empty),
|
|
// Inputs
|
|
.reset (reset),
|
|
.mi_en (mi_en),
|
|
.mi_we (mi_we),
|
|
.mi_addr (mi_addr[RFAW-1:0]),
|
|
.mi_din (mi_din[DW-1:0]));
|
|
|
|
/***********************************************************/
|
|
/*AXI-LITE READBACK */
|
|
/***********************************************************/
|
|
//TODO: fix decode logic
|
|
|
|
assign mi_rd_data[31:0] = (mi_addr[15:14]==2'b00) ? mi_dout_ecfg[31:0] :
|
|
(mi_addr[15:14]==2'b01) ? mi_dout_embox[31:0] :
|
|
(mi_addr[15:14]==2'b10) ? mi_dout_rx[31:0] :
|
|
mi_dout_tx[31:0] ;
|
|
|
|
endmodule // elink
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../../embox/hdl" "../../erx/hdl" "../../etx/hdl" "../../emaxi/hdl" "../../esaxi/hdl" "../../esaxilite/hdl" )
|
|
// End:
|
|
|