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61 lines
1.3 KiB
Verilog
61 lines
1.3 KiB
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, clkout, wait_out, access_out, packet_out,
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// Inputs
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clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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parameter N = 1;
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parameter PW = 104;
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//clock, reset
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input clk1;
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input clk2;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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output clkout;
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transactoin
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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/*AUTOWIRE*/
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wire [31:0] gray;
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//tie offs for Dv
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assign dut_active = 1'b1;
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assign wait_out = 1'b0;
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assign clkout = clk1;
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assign access_out = access_in;
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//convert binary to gray
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oh_bin2gray #(.DW(32))
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b2g (.gray (gray[31:0]),
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.bin (packet_in[39:8]));
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//convert gray back to binary
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oh_gray2bin #(.DW(32))
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g2b(.bin (packet_out[39:8]),
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.gray (gray[31:0]));
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//check for error
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assign error = |(packet_in[39:8] ^ packet_out[39:8]);
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endmodule // dut
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
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// End:
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