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269 lines
9.1 KiB
Verilog
269 lines
9.1 KiB
Verilog
/*
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########################################################################
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ELINK CONFIGURATION REGISTER FILE
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########################################################################
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*/
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module ecfg (/*AUTOARG*/
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// Outputs
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soft_reset, mi_dout, ecfg_tx_enable, ecfg_tx_mmu_enable,
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ecfg_tx_gpio_enable, ecfg_tx_ctrlmode, ecfg_timeout_enable,
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ecfg_rx_enable, ecfg_rx_mmu_enable, ecfg_rx_gpio_enable,
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ecfg_clk_settings, ecfg_coreid, ecfg_dataout,
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// Inputs
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hard_reset, mi_clk, mi_en, mi_we, mi_addr, mi_din, ecfg_rx_datain,
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ecfg_tx_datain, embox_not_empty, embox_full, ecfg_tx_debug,
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ecfg_rx_debug
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);
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/******************************/
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/*Compile Time Parameters */
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/******************************/
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parameter RFAW = 5; // 32 registers for now
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parameter DEFAULT_COREID = 12'h808; // reset value for ecfg_coreid
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parameter DEFAULT_VERSION = 16'h0000; // reset value for version
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parameter DEFAULT_CLKDIV = 4'd7;
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/******************************/
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/*HARDWARE RESET (EXTERNAL) */
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/******************************/
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input hard_reset; // ecfg registers reset only by "hard reset"
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output soft_reset; // soft reset output driven by register
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/*****************************/
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/*SIMPLE MEMORY INTERFACE */
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/*****************************/
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input mi_clk;
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input mi_en;
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input mi_we; // single we, must write 32 bit words
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input [19:0] mi_addr; // complete physical address (no shifting!)
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input [31:0] mi_din;
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output [31:0] mi_dout;
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/*****************************/
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/*ELINK CONTROL SIGNALS */
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/*****************************/
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//reset
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//tx
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output ecfg_tx_enable; // enable signal for TX
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output ecfg_tx_mmu_enable; // enables MMU on transmit path
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output ecfg_tx_gpio_enable; // forces TX output pins to constants
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output [3:0] ecfg_tx_ctrlmode; // value for emesh ctrlmode tag
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output ecfg_timeout_enable; // enables axi slave timeout circuit
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//rx
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output ecfg_rx_enable; // enable signal for rx
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output ecfg_rx_mmu_enable; // enables MMU on rx path
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output ecfg_rx_gpio_enable; // forces rx wait pins to constants
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//clocks
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output [15:0] ecfg_clk_settings; // clock settings
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//coreid
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output [11:0] ecfg_coreid; // core-id of fpga elink
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//gpio
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input [8:0] ecfg_rx_datain; // frame and data
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input [1:0] ecfg_tx_datain; // wait signals
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output [10:0] ecfg_dataout; // data for elink outputs
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//debug
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input embox_not_empty; // not-empty interrupt
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input embox_full; // full debug signal
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input [15:0] ecfg_tx_debug; // etx debug signals
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input [15:0] ecfg_rx_debug; // etx debug signals
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/*------------------------CODE BODY---------------------------------------*/
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//registers
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reg ecfg_reset_reg;
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reg [8:0] ecfg_tx_reg;
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reg [4:0] ecfg_rx_reg;
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reg [15:0] ecfg_clk_reg;
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reg [11:0] ecfg_coreid_reg;
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reg [15:0] ecfg_version_reg;
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reg [10:0] ecfg_datain_reg;
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reg [10:0] ecfg_dataout_reg;
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reg [7:0] ecfg_debug_reg;
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reg [31:0] mi_dout;
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//wires
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wire ecfg_read;
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wire ecfg_write;
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wire ecfg_match;
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wire ecfg_regmux;
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wire [31:0] ecfg_reg_mux;
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wire ecfg_tx_write;
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wire ecfg_rx_write;
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wire ecfg_clk_write;
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wire ecfg_coreid_write;
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wire ecfg_version_write;
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wire ecfg_dataout_write;
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wire ecfg_reset_write;
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wire [31:0] ecfg_debug_vector;
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/*****************************/
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/*ADDRESS DECODE LOGIC */
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/*****************************/
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//read/write decode
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assign ecfg_write = mi_en & mi_we;
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assign ecfg_read = mi_en & ~mi_we;
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//Config write enables
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assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELRESET);
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assign ecfg_clk_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELCLK);
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assign ecfg_tx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTX);
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assign ecfg_rx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELRX);
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assign ecfg_coreid_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELCOREID);
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assign ecfg_dataout_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELDATAOUT);
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assign ecfg_version_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELVERSION);
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//###########################
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//# RESET
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//###########################
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always @ (posedge mi_clk)
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if(hard_reset)
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ecfg_reset_reg <= 1'b0;
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else if (ecfg_reset_write)
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ecfg_reset_reg <= mi_din[0];
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assign soft_reset = ecfg_reset_reg;
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//###########################
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//# TX
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//###########################
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always @ (posedge mi_clk)
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if(hard_reset)
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ecfg_tx_reg[8:0] <= 9'b0;
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else if (ecfg_tx_write)
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ecfg_tx_reg[8:0] <= mi_din[8:0];
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assign ecfg_tx_enable = ecfg_tx_reg[0];
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assign ecfg_tx_mmu_enable = ecfg_tx_reg[1];
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assign ecfg_tx_gpio_enable = (ecfg_tx_reg[3:2]==2'b01);
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assign ecfg_tx_ctrlmode[3:0] = ecfg_tx_reg[7:4];
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assign ecfg_timeout_enable = ecfg_tx_reg[8];
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//###########################
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//# RX
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//###########################
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always @ (posedge mi_clk)
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if(hard_reset)
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ecfg_rx_reg[4:0] <= 5'b0;
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else if (ecfg_rx_write)
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ecfg_rx_reg[4:0] <= mi_din[4:0];
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assign ecfg_rx_enable = ecfg_rx_reg[0];
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assign ecfg_rx_mmu_enable = ecfg_rx_reg[1];
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assign ecfg_rx_gpio_enable = ecfg_rx_reg[3:2]==2'b01;
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//###########################
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//# CCLK/LCLK (PLL)
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//###########################
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always @ (posedge mi_clk)
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if(hard_reset)
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ecfg_clk_reg[15:0] <= 'd0;
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else if (ecfg_clk_write)
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ecfg_clk_reg[15:0] <= mi_din[15:0];
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assign ecfg_clk_settings[15:0] = ecfg_clk_reg[15:0];
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//assign ecfg_cclk_en = ~(ecfg_clk_reg[3:0]==4'b0000);
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//assign ecfg_cclk_div[3:0] = ecfg_clk_reg[3:0];
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//assign ecfg_cclk_pllcfg[3:0] = ecfg_clk_reg[7:4];
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//assign ecfg_cclk_bypass = ecfg_clk_reg[8];
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//###########################
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//# COREID
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//###########################
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always @ (posedge mi_clk)
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if(hard_reset)
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ecfg_coreid_reg[11:0] <= DEFAULT_COREID;
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else if (ecfg_coreid_write)
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ecfg_coreid_reg[11:0] <= mi_din[11:0];
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assign ecfg_coreid[11:0] = ecfg_coreid_reg[11:0];
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//###########################
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//# VERSION
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//###########################
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always @ (posedge mi_clk)
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if(hard_reset)
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ecfg_version_reg[15:0] <= DEFAULT_VERSION;
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else if (ecfg_version_write)
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ecfg_version_reg[15:0] <= mi_din[15:0];
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//###########################
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//# DATAIN
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//###########################
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always @ (posedge mi_clk)
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ecfg_datain_reg[10:0] <= {ecfg_rx_datain[1:0], ecfg_rx_datain[8:0]};
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//###########################
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//# DATAOUT
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//###########################
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always @ (posedge mi_clk)
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if(hard_reset)
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ecfg_dataout_reg[10:0] <= 11'd0;
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else if (ecfg_dataout_write)
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ecfg_dataout_reg[10:0] <= mi_din[10:0];
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assign ecfg_dataout[10:0] = ecfg_dataout_reg[10:0];
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//###########################1
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//# DEBUG
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//###########################
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assign ecfg_debug_vector[31:0]= {embox_not_empty,
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ecfg_rx_debug[14:3],
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ecfg_tx_debug[14:3],
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ecfg_rx_debug[2:0],
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ecfg_tx_debug[2:0],
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embox_full
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};
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always @ (posedge mi_clk)
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if(hard_reset)
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ecfg_debug_reg[7:0] <= 8'd0;
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else
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ecfg_debug_reg[7:0] <=ecfg_debug_reg[7:0] | ecfg_debug_vector[7:0];
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//###############################
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//# DATA READBACK MUX
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//###############################
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//Pipelineing readback
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always @ (posedge mi_clk)
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if(ecfg_read)
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case(mi_addr[RFAW+1:2])
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`ELRESET: mi_dout[31:0] <= {31'b0, ecfg_reset_reg};
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`ELTX: mi_dout[31:0] <= {23'b0, ecfg_tx_reg[8:0]};
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`ELRX: mi_dout[31:0] <= {27'b0, ecfg_rx_reg[4:0]};
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`ELCLK: mi_dout[31:0] <= {24'b0, ecfg_clk_reg[7:0]};
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`ELCOREID: mi_dout[31:0] <= {20'b0, ecfg_coreid_reg[11:0]};
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`ELVERSION: mi_dout[31:0] <= {16'b0, ecfg_version_reg[15:0]};
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`ELDATAIN: mi_dout[31:0] <= {21'b0, ecfg_datain_reg[10:0]};
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`ELDATAOUT: mi_dout[31:0] <= {21'b0, ecfg_dataout_reg[10:0]};
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`ELDEBUG: mi_dout[31:0] <= {ecfg_debug_vector[31:8],ecfg_debug_reg[7:0]};
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default: mi_dout[31:0] <= 32'd0;
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endcase
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endmodule // ecfg
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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