FPGA/oh

mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00

Go to file

Andreas Olofsson ccad681b0e Fixing testbench for new clocks

- Yay! Lots of logic removed
- elink passes again!!!

2015-10-07 19:21:36 -04:00

common

Changing default to simplify instantiation

2015-05-14 22:46:23 -04:00

edma

Moving back to async reset

2015-10-07 19:21:04 -04:00

elink

Fixing testbench for new clocks

2015-10-07 19:21:36 -04:00

emailbox

Moving back to async reset

2015-10-07 19:21:04 -04:00

emesh

Fifo cleanup

2015-07-02 16:59:38 -04:00

emmu

Moving back to async reset

2015-10-07 19:21:04 -04:00

include

Add ip generation helper script

2015-07-05 19:40:30 +02:00

memory

Moving back to async reset

2015-10-07 19:21:04 -04:00

parallella/package/xilinx

Adding parallella block design

2015-05-22 21:38:39 -04:00

xilibs

Adding hack model for RDY signal

2015-10-07 19:18:54 -04:00

.gitignore

Adding register access from RX

2015-04-27 23:51:00 -04:00

configure

Add configure script

2015-07-05 23:30:55 +02:00

CONTRIBUTING.md

Basic infrastructure

2015-04-21 21:36:37 -04:00

COPYING

Basic infrastructure

2015-04-21 21:36:37 -04:00

Makefile.in

Add configure script

2015-07-05 23:30:55 +02:00

README.md

Update README

2015-07-05 23:32:28 +02:00

README.md

=======

OH!

Open Hardware (Pure and Simple)

(work in progress...)

Building

git clone https://github.com/parallella/oh.git
cd oh
mkdir build
cd build
../configure
make elink

Languages

Verilog 81.1%

Tcl 10.7%

C 5.6%

Shell 0.8%

Python 0.6%

Other 1.2%