Andreas Olofsson 028bf19382 TX clock and reset cleanup ...

- more modular
- two bits cominng from sys_clk elink config domain
- drives the tx and rx from top level elink
- from software you would probably write 2'b11 to reset both at same time

2015-10-07 19:15:29 -04:00

..

axi_elink.v

TX clock and reset cleanup

2015-10-07 19:15:29 -04:00

ecfg_elink.v

TX clock and reset cleanup

2015-10-07 19:15:29 -04:00

ecfg_if.v

TX clock and reset cleanup

2015-10-07 19:15:29 -04:00

eclocks.v

Making reset async

2015-10-07 14:46:12 -04:00

elink_constants.v

Removing ephycard define

2015-08-25 12:40:48 +02:00

elink_regmap.v

Adding software programmable IDELAY

2015-10-07 11:49:46 -04:00

elink.v

TX clock and reset cleanup

2015-10-07 19:15:29 -04:00

emaxi.v

Making reset async

2015-10-07 14:46:12 -04:00

ereset.v

Adding software programmable IDELAY

2015-10-07 11:49:46 -04:00

erx_arbiter.v

Fixing mutual exclusive bug on receiver

2015-08-14 15:37:37 -04:00

erx_cfg.v

RX reset/clocking cleanup

2015-10-07 19:12:57 -04:00

erx_clocks.v

Separating clocks for tx/rx

2015-10-07 19:08:32 -04:00

erx_core.v

RX reset/clocking cleanup

2015-10-07 19:12:57 -04:00

erx_fifo.v

Copyright cleanup

2015-08-07 09:19:37 -04:00

erx_io.v

RX reset/clocking cleanup

2015-10-07 19:12:57 -04:00

erx_protocol.v

RX reset/clocking cleanup

2015-10-07 19:12:57 -04:00

erx_remap.v

RX reset/clocking cleanup

2015-10-07 19:12:57 -04:00

erx_timer.v

Converting to synchronous reset

2015-05-17 23:00:53 -04:00

erx.v

RX reset/clocking cleanup

2015-10-07 19:12:57 -04:00

esaxi.v

Making reset async

2015-10-07 14:46:12 -04:00

etx_arbiter.v

Fixing mutual exclusive bug on receiver

2015-08-14 15:37:37 -04:00

etx_cfg.v

Removing DMA from transmit

2015-08-07 09:05:11 -04:00

etx_clocks.v

Separating clocks for tx/rx

2015-10-07 19:08:32 -04:00

etx_core.v

Removing DMA from transmit

2015-08-07 09:05:11 -04:00

etx_fifo.v

Fifo parameter change

2015-07-02 16:55:42 -04:00

etx_io.v

Cleaning up TX reset

2015-10-07 19:12:01 -04:00

etx_protocol.v

Fixing wait issue

2015-08-14 17:13:52 -04:00

etx_remap.v

Separate rd/wr stalls

2015-05-04 17:09:50 -04:00

etx.v

TX clock and reset cleanup

2015-10-07 19:15:29 -04:00