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291 lines
7.8 KiB
Verilog
291 lines
7.8 KiB
Verilog
`include "elink_constants.v"
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module etx_io (/*AUTOARG*/
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// Outputs
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait,
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// Inputs
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reset, tx_lclk, tx_lclk90, txi_wr_wait_p, txi_wr_wait_n,
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txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access, tx_burst
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);
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parameter IOSTD_ELINK = "LVDS_25";
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parameter PW = 104;
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parameter ETYPE = 1;//0=parallella
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//1=ephycard
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//###########
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//# reset, clocks
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//##########
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input reset; //sync reset for io
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input tx_lclk; //fast clock for io
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input tx_lclk90; //fast 90deg shifted lclk
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//###########
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//# eLink pins
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//###########
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output txo_lclk_p, txo_lclk_n; // tx clock output
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output txo_frame_p, txo_frame_n; // tx frame signal
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output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
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input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback
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input txi_rd_wait_p, txi_rd_wait_n; // tx read pushback
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//#############
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//# Fabric interface
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//#############
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input [PW-1:0] tx_packet;
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input tx_access;
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input tx_burst;
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output tx_io_wait;
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output tx_wr_wait;
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output tx_rd_wait;
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//############
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//# REGS
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//############
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reg [7:0] tx_pointer;
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reg [15:0] tx_data16;
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reg tx_access_reg;
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reg tx_frame;
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reg tx_io_wait_reg;
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reg [PW-1:0] tx_packet_reg;
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reg [63:0] tx_double;
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reg [2:0] tx_state_reg;
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reg [2:0] tx_state;
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//############
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//# WIRES
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//############
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wire new_tran;
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wire access;
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wire write;
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wire [1:0] datamode;
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wire [3:0] ctrlmode;
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wire [31:0] dstaddr;
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wire [31:0] data;
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wire [31:0] srcaddr;
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wire [7:0] txo_data;
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wire txo_frame;
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wire txo_lclk90;
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reg tx_io_wait;
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//#############################
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//# Transmit state machine
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//#############################
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`define IDLE 3'b000
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`define CYCLE1 3'b001
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`define CYCLE2 3'b010
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`define CYCLE3 3'b011
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`define CYCLE4 3'b100
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`define CYCLE5 3'b101
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`define CYCLE6 3'b110
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`define CYCLE7 3'b111
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always @ (posedge tx_lclk)
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if(reset)
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tx_state[2:0] <= `IDLE;
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else
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case (tx_state[2:0])
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`IDLE : tx_state[2:0] <= tx_access ? `CYCLE1 : `IDLE;
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`CYCLE1 : tx_state[2:0] <= `CYCLE2;
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`CYCLE2 : tx_state[2:0] <= `CYCLE3;
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`CYCLE3 : tx_state[2:0] <= `CYCLE4;
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`CYCLE4 : tx_state[2:0] <= `CYCLE5;
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`CYCLE5 : tx_state[2:0] <= `CYCLE6;
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`CYCLE6 : tx_state[2:0] <= `CYCLE7;
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`CYCLE7 : tx_state[2:0] <= tx_burst ? `CYCLE4 : `IDLE;
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endcase // case (tx_state)
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assign tx_new_frame = (tx_state[2:0]==`CYCLE1);
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//Creating wait pulse for slow clock domain
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always @ (posedge tx_lclk)
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if(reset | ~tx_access)
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tx_io_wait <= 1'b0;
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else if ((tx_state[2:0] ==`CYCLE4) & ~tx_burst)
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tx_io_wait <= 1'b1;
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else if (tx_state[2:0]==`CYCLE7)
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tx_io_wait <= 1'b0;
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//Create frame signal for output
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always @ (posedge tx_lclk)
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begin
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tx_state_reg[2:0] <= tx_state[2:0];
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tx_frame <= |(tx_state_reg[2:0]);
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end
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//#############################
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//# 2 CYCLE PACKET PIPELINE
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//#############################
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always @ (posedge tx_lclk)
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if (tx_access)
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tx_packet_reg[PW-1:0] <= tx_packet[PW-1:0];
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packet2emesh p2e (.access_out (access),
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.write_out (write),
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.datamode_out (datamode[1:0]),
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.ctrlmode_out (ctrlmode[3:0]),
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.dstaddr_out (dstaddr[31:0]),
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.data_out (data[31:0]),
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.srcaddr_out (srcaddr[31:0]),
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.packet_in (tx_packet_reg[PW-1:0]));
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always @ (posedge tx_lclk)
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if (tx_new_frame)
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tx_double[63:0] <= {16'b0,//16
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~write,7'b0,ctrlmode[3:0],//12
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dstaddr[31:0],datamode[1:0],write,access};//36
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else if(tx_state[2:0]==`CYCLE4)
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tx_double[63:0] <= {data[31:0],srcaddr[31:0]};
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//#############################
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//# SELECTING DATA FOR TRANSMIT
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//#############################
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always @ (posedge tx_lclk)
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case(tx_state_reg[2:0])
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//Cycle1
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3'b001: tx_data16[15:0] <= tx_double[47:32];
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//Cycle2
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3'b010: tx_data16[15:0] <= tx_double[31:16];
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//Cycle3
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3'b011: tx_data16[15:0] <= tx_double[15:0];
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//Cycle4
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3'b100: tx_data16[15:0] <= tx_double[63:48];
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//Cycle5
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3'b101: tx_data16[15:0] <= tx_double[47:32];
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//Cycle6
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3'b110: tx_data16[15:0] <= tx_double[31:16];
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//Cycle7
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3'b111: tx_data16[15:0] <= tx_double[15:0];
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default tx_data16[15:0] <= 16'b0;
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endcase // case (tx_state[2:0])
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//#############################
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//# ODDR DRIVERS
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//#############################
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//DATA
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genvar i;
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generate for(i=0; i<8; i=i+1)
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begin : gen_oddr
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
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oddr_data (
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.Q (txo_data[i]),
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.C (tx_lclk),
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.CE (1'b1),
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.D1 (tx_data16[i+8]),
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.D2 (tx_data16[i]),
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.R (1'b0),
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.S (1'b0)
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);
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end
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endgenerate
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//FRAME
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE ("SYNC"))
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oddr_frame (
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.Q (txo_frame),
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.C (tx_lclk),
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.CE (1'b1),
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.D1 (tx_frame),
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.D2 (tx_frame),
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.R (reset),
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.S (1'b0)
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);
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//LCLK
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
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oddr_lclk (
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.Q (txo_lclk90),
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.C (tx_lclk90),
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.CE (1'b1),
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.D1 (1'b1),
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.D2 (1'b0),
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.R (reset),//should be no reason to reset clock, static input
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.S (1'b0)
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);
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//##############################
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//# OUTPUT BUFFERS
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//##############################
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OBUFDS obufds_data[7:0] (
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.O (txo_data_p[7:0]),
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.OB (txo_data_n[7:0]),
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.I (txo_data[7:0])
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);
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OBUFDS obufds_frame ( .O (txo_frame_p),
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.OB (txo_frame_n),
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.I (txo_frame)
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);
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OBUFDS obufds_lclk ( .O (txo_lclk_p),
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.OB (txo_lclk_n),
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.I (txo_lclk90)
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);
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//################################
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//# Wait Input Buffers
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//################################
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generate
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if(ETYPE==1)
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begin
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assign tx_wr_wait = txi_wr_wait_p;
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end
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else if (ETYPE==0)
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begin
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IBUFDS
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#(.DIFF_TERM ("TRUE"), // Differential termination
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.IOSTANDARD (IOSTD_ELINK))
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ibufds_wrwait
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(.I (txi_wr_wait_p),
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.IB (txi_wr_wait_n),
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.O (tx_wr_wait));
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end
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endgenerate
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//TODO: Come up with cleaner defines for this
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//Parallella and other platforms...
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`ifdef TODO
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IBUFDS
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#(.DIFF_TERM ("TRUE"), // Differential termination
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.IOSTANDARD (IOSTD_ELINK))
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ibufds_rdwait
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(.I (txi_rd_wait_p),
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.IB (txi_rd_wait_n),
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.O (tx_rd_wait));
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`else
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//On Parallella this signal comes in single-ended
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assign tx_rd_wait = txi_rd_wait_p;
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`endif
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endmodule // etx_io
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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Contributed by Gunnar Hillerstrom
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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