Andreas Olofsson c627827a6b Fifo cleanup ...

-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules

2015-07-02 16:59:38 -04:00

..

dv

Reorg

2015-06-25 19:52:28 -04:00

hdl

Fifo cleanup

2015-07-02 16:59:38 -04:00