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- Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock. - Moving the clock block into the RX for modularity - Making a specil rx soft reset (driven from sys_clk domain) - Still there is a POR_reset so the link should wake up ok
87 lines
2.4 KiB
Verilog
87 lines
2.4 KiB
Verilog
module erx_remap (/*AUTOARG*/
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// Outputs
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emesh_access_out, emesh_packet_out,
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// Inputs
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clk, reset, emesh_access_in, emesh_packet_in, remap_mode,
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remap_sel, remap_pattern, remap_base
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 12'h808;
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//Clock/reset
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input clk;
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input reset; //async reset
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//Input from arbiter
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input emesh_access_in;
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input [PW-1:0] emesh_packet_in;
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//Configuration
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input [1:0] remap_mode; //00=none,01=static,02=continuity
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input [11:0] remap_sel; //number of bits to remap
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input [11:0] remap_pattern; //static pattern to map to
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input [31:0] remap_base; //remap offset
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//Output to TX IO
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output emesh_access_out;
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output [PW-1:0] emesh_packet_out;
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wire [31:0] static_remap;
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wire [31:0] dynamic_remap;
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wire [31:0] remap_mux;
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wire write_in;
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wire read_in;
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wire [31:0] addr_in;
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wire [31:0] addr_out;
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wire remap_en;
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reg emesh_access_out;
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reg [PW-1:0] emesh_packet_out;
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//TODO:FIX!??
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parameter[5:0] colid = ID[5:0];
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//parsing packet
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assign addr_in[31:0] = emesh_packet_in[39:8];
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assign write_in = emesh_packet_in[1];
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assign read_in = ~emesh_packet_in[1];
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//simple static remap
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assign static_remap[31:20] = (remap_sel[11:0] & remap_pattern[11:0]) |
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(~remap_sel[11:0] & addr_in[31:20]);
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assign static_remap[19:0] = addr_in[19:0];
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//more complex compresssed map
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assign dynamic_remap[31:0] = addr_in[31:0] //input
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- (colid << 20) //subtracing elink (start at 0)
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+ remap_base[31:0] //adding back base
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- (addr_in[31:26]<<$clog2(colid));
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//Static, dynamic, or no remap
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assign remap_mux[31:0] = (remap_mode[1:0]==2'b00) ? addr_in[31:0] :
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(remap_mode[1:0]==2'b01) ? static_remap[31:0] :
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dynamic_remap[31:0];
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//Access
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always @ (posedge clk or posedge reset)
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if (reset)
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emesh_access_out <= 1'b0;
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else
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emesh_access_out <= emesh_access_in;
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//Packet
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always @ (posedge clk)
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emesh_packet_out[PW-1:0] <= {emesh_packet_in[103:40],
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remap_mux[31:0],
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emesh_packet_in[7:0]
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};
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endmodule // etx_mux
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