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35 lines
1.4 KiB
Markdown
35 lines
1.4 KiB
Markdown
CHIP DESIGN REFERENCE FLOW
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This folder contains the recommended directory structure for implementing ASICs using OH! The directory structure is based on two decades of chip design experience (from 0.35um to 14nm) and is currently being used by Adapteva to design Epiphany based ASICs.
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The structure is designed to simplify implementation scripts and maximize portability across:
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* multiple foundries
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* multiple process nodes
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* multiple IP vendors
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* multiple EDA vendors
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## RESOURCES
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* [Glossary](docs/glossary.md)
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* [Constants](docs/constants.md)
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## DIRECTORY STRUCTURE & NAMING METHODOLOGY
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* **docs**: Common documents and design guidelines
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* **foundry name ("foundry1")**: tsmc, gf, tower, smic, umc, etc
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* **process name ("process1")**: 28slp, 65g, etc
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* **hard ip name**: pdk, stdlib, io, sram, serdes, etc
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* **IP company name ("ipco1")**: arm, synopsys, cadence, tsmc, etc
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* **eda name ("eda1")**: synopsys, cadence, mentor, etc
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Description of contents inside each folder can be found in the local README.md file.
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To visualize the directory structure, use the 'tree' utility.
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## CONTRIBUTION NEEDED
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Non-disclosure agreements prevent populating the directory with exact script and process details. If you have access to an open process, then please do subnmit a PR with a populated technology tree
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