mirror of
https://github.com/aolofsson/oh.git
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3ce9b41726
- Gating mailbox_not empty with irq_en. bit [28] of RXCFG - Changing elink output interrupt to "or" of not_empty and full - Adding mailbox status register (mostly for debug) - Moving register addresses to make space for mailbox status register - Fixing wrappers for DV - Updating README docs with new register map - Removing mailbox from RX status reg. Doesn't belong there, should be coupled with mailbox for modularity.
326 lines
13 KiB
Verilog
326 lines
13 KiB
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, wait_out, access_out, packet_out,
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// Inputs
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elink1_txo_lclk_p, elink1_txo_lclk_n, elink1_txo_frame_p,
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elink1_txo_frame_n, elink1_txo_data_p, elink1_txo_data_n,
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elink1_rxo_wr_wait_p, elink1_rxo_wr_wait_n, elink1_rxo_rd_wait_p,
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elink1_rxo_rd_wait_n, clk, nreset, vdd, vss, access_in, packet_in,
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wait_in
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2;
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parameter IDW = 12;
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parameter M_IDW = 6;
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parameter S_IDW = 12;
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parameter PW = 104;
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parameter N = 1;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transactoin
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input elink1_rxo_rd_wait_n; // To elink0 of elink.v
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input elink1_rxo_rd_wait_p; // To elink0 of elink.v
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input elink1_rxo_wr_wait_n; // To elink0 of elink.v
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input elink1_rxo_wr_wait_p; // To elink0 of elink.v
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input [7:0] elink1_txo_data_n; // To elink0 of elink.v
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input [7:0] elink1_txo_data_p; // To elink0 of elink.v
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input elink1_txo_frame_n; // To elink0 of elink.v
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input elink1_txo_frame_p; // To elink0 of elink.v
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input elink1_txo_lclk_n; // To elink0 of elink.v
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input elink1_txo_lclk_p; // To elink0 of elink.v
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// End of automatics
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//floating wires
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wire elink0_cclk_n; // From elink0 of elink.v
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wire elink0_cclk_p; // From elink0 of elink.v
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wire elink0_chip_resetb; // From elink0 of elink.v
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wire [11:0] elink0_chipid; // From elink0 of elink.v
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wire elink0_mailbox_full; // From elink0 of elink.v
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wire elink0_mailbox_not_empty;// From elink0 of elink.v
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wire elink0_timeout; // From elink0 of elink.v
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wire elink1_cclk_n; // From elink1 of elink.v
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wire elink1_cclk_p; // From elink1 of elink.v
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wire elink1_chip_resetb; // From elink1 of elink.v
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wire [11:0] elink1_chipid; // From elink1 of elink.v
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wire elink1_mailbox_full; // From elink1 of elink.v
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wire elink1_mailbox_not_empty;// From elink1 of elink.v
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wire elink1_rxrd_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxrd_packet; // From elink1 of elink.v
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wire elink1_rxrr_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxrr_packet; // From elink1 of elink.v
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wire elink1_rxwr_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxwr_packet; // From elink1 of elink.v
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wire elink1_timeout; // From elink1 of elink.v
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wire elink1_txrd_wait; // From elink1 of elink.v
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wire elink1_txrr_access; // From emem of ememory.v
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wire [PW-1:0] elink1_txrr_packet; // From emem of ememory.v
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wire elink1_txrr_wait; // From elink1 of elink.v
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wire elink1_txwr_wait; // From elink1 of elink.v
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//memory wires
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wire emem_access;
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wire [PW-1:0] emem_packet;
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// Beginning of automatic outputs (from unused autoinst outputs)
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire elink0_chip_nreset; // From elink0 of elink.v
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wire elink0_mailbox_irq; // From elink0 of elink.v
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wire elink0_rxo_rd_wait_n; // From elink0 of elink.v
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wire elink0_rxo_rd_wait_p; // From elink0 of elink.v
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wire elink0_rxo_wr_wait_n; // From elink0 of elink.v
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wire elink0_rxo_wr_wait_p; // From elink0 of elink.v
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wire elink0_rxrr_access; // From elink0 of elink.v
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wire [PW-1:0] elink0_rxrr_packet; // From elink0 of elink.v
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wire [7:0] elink0_txo_data_n; // From elink0 of elink.v
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wire [7:0] elink0_txo_data_p; // From elink0 of elink.v
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wire elink0_txo_frame_n; // From elink0 of elink.v
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wire elink0_txo_frame_p; // From elink0 of elink.v
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wire elink0_txo_lclk_n; // From elink0 of elink.v
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wire elink0_txo_lclk_p; // From elink0 of elink.v
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wire elink0_txrd_access; // From emesh_if of emesh_if.v
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wire [PW-1:0] elink0_txrd_packet; // From emesh_if of emesh_if.v
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wire elink0_txrd_wait; // From elink0 of elink.v
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wire elink0_txwr_access; // From emesh_if of emesh_if.v
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wire [PW-1:0] elink0_txwr_packet; // From emesh_if of emesh_if.v
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wire elink0_txwr_wait; // From elink0 of elink.v
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// End of automatics
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//######################################################################
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//EMESH INTERFACE
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//######################################################################
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/*emesh_if AUTO_TEMPLATE (//Stimulus
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.e2c_emesh_\(.*\)_in(\1_in[]),
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.e2c_emesh_\(.*\)_out(\1_out[]),
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//Response
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.c2e_emesh_\(.*\)_out(\1_out[]),
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.c2e_emesh_\(.*\)_in(\1_in[]),
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.c2e_cmesh_\(.*\)_in(elink0_rxrr_\1[]),
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//Link side transaction outgoing
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.e2c_cmesh_\(.*\)_out(elink0_txwr_\1[]),
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.e2c_cmesh_wait_in(elink0_txwr_wait),
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.e2c_rmesh_\(.*\)_out(elink0_txrd_\1[]),
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.e2c_rmesh_wait_in(elink0_txrd_wait),
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.c2e_\(.*\)_wait_out(),
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);
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*/
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emesh_if #(.PW(PW)) emesh_if (.c2e_rmesh_access_in(1'b0),
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.c2e_rmesh_packet_in({(PW){1'b0}}),
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.c2e_xmesh_access_in(1'b0),
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.c2e_xmesh_packet_in({(PW){1'b0}}),
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.e2c_xmesh_wait_in(1'b0),
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.e2c_xmesh_access_out(),
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.e2c_xmesh_packet_out(),
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/*AUTOINST*/
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// Outputs
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.c2e_cmesh_wait_out (), // Templated
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.e2c_cmesh_access_out (elink0_txwr_access), // Templated
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.e2c_cmesh_packet_out (elink0_txwr_packet[PW-1:0]), // Templated
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.c2e_rmesh_wait_out (), // Templated
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.e2c_rmesh_access_out (elink0_txrd_access), // Templated
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.e2c_rmesh_packet_out (elink0_txrd_packet[PW-1:0]), // Templated
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.c2e_xmesh_wait_out (), // Templated
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.e2c_emesh_wait_out (wait_out), // Templated
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.c2e_emesh_access_out (access_out), // Templated
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.c2e_emesh_packet_out (packet_out[PW-1:0]), // Templated
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// Inputs
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.c2e_cmesh_access_in (elink0_rxrr_access), // Templated
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.c2e_cmesh_packet_in (elink0_rxrr_packet[PW-1:0]), // Templated
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.e2c_cmesh_wait_in (elink0_txwr_wait), // Templated
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.e2c_rmesh_wait_in (elink0_txrd_wait), // Templated
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.e2c_emesh_access_in (access_in), // Templated
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.e2c_emesh_packet_in (packet_in[PW-1:0]), // Templated
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.c2e_emesh_wait_in (wait_in)); // Templated
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//######################################################################
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//1ST ELINK
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//######################################################################
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/*elink AUTO_TEMPLATE (
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// Outputs
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.sys_clk (clk),
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.sys_nreset (nreset),
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.rxi_\(.*\) (elink1_txo_\1[]),
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.txi_\(.*\) (elink1_rxo_\1[]),
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.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
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);
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*/
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defparam elink0.ID = 12'h810;
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defparam elink0.ETYPE = 0;
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elink elink0 (.elink_active (dut_active),
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.txrr_access (1'b0),//not tested
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.txrr_packet ({(PW){1'b0}}),
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.txrr_wait (), //not tested
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.rxwr_access (),
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.rxwr_packet (),
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.rxrd_access (),
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.rxrd_packet (),
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.rxwr_wait (1'b0),//not tested
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.rxrd_wait (1'b0),//not tested
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.rxrr_wait (1'b0),//not tested
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/*AUTOINST*/
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// Outputs
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.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
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.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
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.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
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.rxo_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
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.txo_lclk_p (elink0_txo_lclk_p), // Templated
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.txo_lclk_n (elink0_txo_lclk_n), // Templated
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.txo_frame_p (elink0_txo_frame_p), // Templated
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.txo_frame_n (elink0_txo_frame_n), // Templated
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.txo_data_p (elink0_txo_data_p[7:0]), // Templated
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.txo_data_n (elink0_txo_data_n[7:0]), // Templated
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.chipid (elink0_chipid[11:0]), // Templated
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.cclk_p (elink0_cclk_p), // Templated
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.cclk_n (elink0_cclk_n), // Templated
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.chip_nreset (elink0_chip_nreset), // Templated
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.mailbox_irq (elink0_mailbox_irq), // Templated
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.rxrr_access (elink0_rxrr_access), // Templated
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.rxrr_packet (elink0_rxrr_packet[PW-1:0]), // Templated
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.txwr_wait (elink0_txwr_wait), // Templated
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.txrd_wait (elink0_txrd_wait), // Templated
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// Inputs
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.sys_nreset (nreset), // Templated
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.sys_clk (clk), // Templated
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.rxi_lclk_p (elink1_txo_lclk_p), // Templated
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.rxi_lclk_n (elink1_txo_lclk_n), // Templated
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.rxi_frame_p (elink1_txo_frame_p), // Templated
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.rxi_frame_n (elink1_txo_frame_n), // Templated
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.rxi_data_p (elink1_txo_data_p[7:0]), // Templated
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.rxi_data_n (elink1_txo_data_n[7:0]), // Templated
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.txi_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
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.txi_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
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.txi_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
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.txi_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
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.txwr_access (elink0_txwr_access), // Templated
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.txwr_packet (elink0_txwr_packet[PW-1:0]), // Templated
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.txrd_access (elink0_txrd_access), // Templated
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.txrd_packet (elink0_txrd_packet[PW-1:0])); // Templated
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//######################################################################
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//2ND ELINK (E16 REFERENCE MODEL)
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//######################################################################
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wire emem_wait;
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assign elink1_rxo_wr_wait_n = ~elink1_rxo_wr_wait_p;
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assign elink1_rxo_rd_wait_n = ~elink1_rxo_rd_wait_p;
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assign elink1_txo_frame_n = ~elink1_txo_frame_p;
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assign elink1_txo_data_n = ~elink1_txo_data_p;
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assign elink1_txo_lclk_n = ~elink1_txo_lclk_p;
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elink_e16 elink_ref (
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// Outputs
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.rxi_rd_wait (elink1_rxo_rd_wait_p),
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.rxi_wr_wait (elink1_rxo_wr_wait_p),
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.txo_data (elink1_txo_data_p[7:0]),
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.txo_lclk (elink1_txo_lclk_p),
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.txo_frame (elink1_txo_frame_p),
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.c0_mesh_access_out(elink1_rcv_access),
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.c0_mesh_write_out (elink1_rcv_packet[0]),
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.c0_mesh_dstaddr_out(elink1_rcv_packet[39:8]),
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.c0_mesh_srcaddr_out(elink1_rcv_packet[103:72]),
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.c0_mesh_data_out (elink1_rcv_packet[71:40]),
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.c0_mesh_datamode_out(elink1_rcv_packet[2:1]),
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.c0_mesh_ctrlmode_out(elink1_rcv_packet[6:3]),
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.c0_emesh_wait_out (),
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.c0_mesh_wait_out (elink2_wait_out),
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// Inputs
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.reset (~elink0_chip_nreset),
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.c0_clk_in (clk),
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.c1_clk_in (clk),
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.c2_clk_in (clk),
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.c3_clk_in (clk),
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.rxi_data (elink0_txo_data_p[7:0]),
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.rxi_lclk (elink0_txo_lclk_p),
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.rxi_frame (elink0_txo_frame_p),
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.txo_rd_wait (elink0_rxo_rd_wait_p),
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.txo_wr_wait (elink0_rxo_wr_wait_p),
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.c0_mesh_wait_in (emem_wait),//
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.c0_mesh_write_in (elink1_send_packet[0]),
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.c0_mesh_dstaddr_in(elink1_send_packet[39:8]),
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.c0_mesh_srcaddr_in(elink1_send_packet[103:72]),
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.c0_mesh_data_in (elink1_send_packet[71:40]),
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.c0_mesh_datamode_in(elink1_send_packet[2:1]),
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.c0_mesh_ctrlmode_in(elink1_send_packet[6:3])
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);
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wire [103:0] elink1_rcv_packet;
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wire [103:0] elink1_send_packet;
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assign elink1_rcv_packet[7]=1'b0;
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//"Arbitration" between read/write transaction
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assign emem_access = elink1_rcv_access;
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assign emem_packet[PW-1:0] = elink1_rcv_packet;
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/*ememory AUTO_TEMPLATE (
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// Outputs
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.\(.*\)_out (elink1_txrr_\1[]),
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.\(.*\)_in (emem_\1[]),
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.wait_out (emem_wait),
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);
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*/
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defparam emem.WAIT=1;
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ememory emem (.wait_in (1'b0), //TODO: model burst reads!
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.clk (clk),
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.wait_out (emem_wait),
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.coreid (12'h0),
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/*AUTOINST*/
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// Outputs
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.access_out (elink1_txrr_access), // Templated
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.packet_out (elink1_txrr_packet[PW-1:0]), // Templated
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// Inputs
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.nreset (nreset),
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.access_in (emem_access), // Templated
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.packet_in (emem_packet[PW-1:0])); // Templated
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endmodule // dv_elink
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
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// End:
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