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oh/elink/fpga/axi_elink_timing.xdc
Andreas Olofsson 8b2974feae Massive reorg!
- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00

7 lines
167 B
Tcl

#SYS_CLK
create_clock -name sys_clk -period 10 [get_ports sys_clk]
#RECEIVER
create_clock -period 3.333 -name rx_lclk -waveform {0.000 1.667} [get_ports rxi_lclk_p]