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39 lines
1.6 KiB
Verilog
39 lines
1.6 KiB
Verilog
/******************************************************************************
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* Function: Results Checker
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* Author: Andreas Olofsson
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* Copyright: (c) 2020 Adapteva, Inc. All rights reserved.
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* ----------------------------------------------------------------------------
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* License: This file contains confidential and proprietary information of
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* Adapteva. No part of this file may be reproduced, transmitted,
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* transcribed, stored in a retrieval system, or translated into any human or
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* computer language, in any form or by any means, electronic, mechanical,
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* magnetic, optical, chemical, manual, or otherwise, without prior written
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* permission of Adapteva. This software may only be used in accordance with
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* the terms and conditions of a signed license agreement with Adateva. All
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* other use, reproduction or distribution of this software is
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* strictly prohibited.
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* ----------------------------------------------------------------------------
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*
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*****************************************************************************/
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module dv_checker
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(
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//Inputs
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input clk,
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input nreset,
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input [DW-1:0] result, // result to check
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input [DW-1:0] reference, // reference result
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output fail, //fail indicator
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);
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reg fail;
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always @ (negedge clk or negedge nreset)
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if(~nreset)
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fail <= 1'b0;
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else if(result!==reference)
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begin
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fail <= 1'b1;
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$display("ERROR(%0t): result=%b reference=%b", result, reference);
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end
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endmodule // dv_checker
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