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d0b04687ea
-Apparantly old FIFO was not pipelined (IE data comes back same cycle). -Not knowing the Xilinx logic, I made it a regular one cycle pipeline memory based FIFO
431 lines
15 KiB
Verilog
431 lines
15 KiB
Verilog
/*
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########################################################################
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Epiphany eLink AXI Master Module
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########################################################################
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*/
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module emaxi(/*autoarg*/
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// Outputs
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emwr_rd_en, emrq_rd_en, emrr_access, emrr_write, emrr_datamode,
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emrr_ctrlmode, emrr_dstaddr, emrr_data, emrr_srcaddr, m_axi_awid,
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m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
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m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
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m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
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m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
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m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
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m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
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// Inputs
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emwr_access, emwr_write, emwr_datamode, emwr_ctrlmode,
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emwr_dstaddr, emwr_data, emwr_srcaddr, emrq_access, emrq_write,
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emrq_datamode, emrq_ctrlmode, emrq_dstaddr, emrq_data,
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emrq_srcaddr, emrr_progfull, m_axi_aclk, m_axi_aresetn,
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m_axi_awready, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid,
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m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast,
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m_axi_rvalid
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);
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parameter IDW = 12;
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// fifo read-master port, writes from rx
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input emwr_access;
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input emwr_write;
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input [1:0] emwr_datamode;
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input [3:0] emwr_ctrlmode;
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input [31:0] emwr_dstaddr;
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input [31:0] emwr_data;
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input [31:0] emwr_srcaddr;
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output emwr_rd_en; //read ptr update for fifo
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// fifo read-master port; read requests from rx
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input emrq_access;
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input emrq_write;
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input [1:0] emrq_datamode;
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input [3:0] emrq_ctrlmode;
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input [31:0] emrq_dstaddr;
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input [31:0] emrq_data;
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input [31:0] emrq_srcaddr;
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output emrq_rd_en; //read ptr update for fifo
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// fifo write-master port; read responses for etx
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output emrr_access;
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output emrr_write;
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output [1:0] emrr_datamode;
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output [3:0] emrr_ctrlmode;
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output [31:0] emrr_dstaddr;
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output [31:0] emrr_data;
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output [31:0] emrr_srcaddr;
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input emrr_progfull;
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/*****************************/
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/*axi */
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/*****************************/
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input m_axi_aclk; // global clock signal.
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input m_axi_aresetn; // global reset singal.
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//Write address channel
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output [IDW-1:0] m_axi_awid; // write address ID
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output [31 : 0] m_axi_awaddr; // master interface write address
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output [7 : 0] m_axi_awlen; // burst length.
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output [2 : 0] m_axi_awsize; // burst size.
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output [1 : 0] m_axi_awburst; // burst type.
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output [1 : 0] m_axi_awlock; // lock type
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output [3 : 0] m_axi_awcache; // memory type.
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output [2 : 0] m_axi_awprot; // protection type.
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output [3 : 0] m_axi_awqos; // quality of service
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output m_axi_awvalid; // write address valid
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input m_axi_awready; // write address ready
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//Write data channel
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output [IDW-1:0] m_axi_wid;
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output [63 : 0] m_axi_wdata; // master interface write data.
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output [7 : 0] m_axi_wstrb; // byte write strobes
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output m_axi_wlast; // indicates last transfer in a write burst.
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output m_axi_wvalid; // indicates data is ready to go
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input m_axi_wready; // indicates that the slave is ready for data
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//Write response channel
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input [IDW-1:0] m_axi_bid;
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input [1 : 0] m_axi_bresp; // status of the write transaction.
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input m_axi_bvalid; // channel is signaling a valid write response
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output m_axi_bready; // master can accept write response.
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//Read address channel
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output [IDW-1:0] m_axi_arid; // read address ID
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output [31 : 0] m_axi_araddr; // initial address of a read burst
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output [7 : 0] m_axi_arlen; // burst length
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output [2 : 0] m_axi_arsize; // burst size
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output [1 : 0] m_axi_arburst; // burst type
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output [1 : 0] m_axi_arlock; //lock type
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output [3 : 0] m_axi_arcache; // memory type
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output [2 : 0] m_axi_arprot; // protection type
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output [3 : 0] m_axi_arqos; //
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output m_axi_arvalid; // valid read address and control information
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input m_axi_arready; // slave is ready to accept an address
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//Read data channel
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input [IDW-1:0] m_axi_rid;
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input [63 : 0] m_axi_rdata; // master read data
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input [1 : 0] m_axi_rresp; // status of the read transfer
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input m_axi_rlast; // signals last transfer in a read burst
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input m_axi_rvalid; // signaling the required read data
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output m_axi_rready; // master can accept the readback data
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//registers
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reg [31 : 0] m_axi_awaddr;
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reg [7:0] m_axi_awlen;
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reg [2:0] m_axi_awsize;
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reg m_axi_awvalid;
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reg [63 : 0] m_axi_wdata;
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reg [7 : 0] m_axi_wstrb;
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reg m_axi_wlast;
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reg m_axi_wvalid;
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reg awvalid_b;
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reg [31:0] awaddr_b;
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reg [2:0] awsize_b;
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reg [7:0] awlen_b;
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reg wvalid_b;
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reg [63:0] wdata_b;
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reg [7:0] wstrb_b;
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reg [63 : 0] wdata_aligned;
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reg [7 : 0] wstrb_aligned;
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reg emrr_access;
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reg emrr_access_reg;
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reg [31:0] emrr_data;
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reg [31:0] emrr_srcaddr;
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//wires
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wire aw_go;
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wire w_go;
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wire readinfo_wren;
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wire readinfo_rden;
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wire readinfo_full;
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wire [47:0] readinfo_out;
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wire [47:0] readinfo_in;
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//i/o connections. write address (aw)
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assign m_axi_awburst[1:0] = 2'b01;
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assign m_axi_awcache[3:0] = 4'b0010;//TODO??update value to 4'b0011 if coherent accesses to be used via the zynq acp port
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assign m_axi_awprot[2:0] = 3'h0;
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assign m_axi_awqos[3:0] = 4'h0;
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assign m_axi_bready = 1'b1; //TODO? axi_bready, why constant
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assign m_axi_arburst[1:0] = 2'b01;
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assign m_axi_arcache[3:0] = 4'b0010;
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assign m_axi_arprot[2:0] = 3'h0;
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assign m_axi_arqos[3:0] = 4'h0;
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//--------------------
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//write address channel
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//--------------------
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assign aw_go = m_axi_awvalid & m_axi_awready;
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assign w_go = m_axi_wvalid & m_axi_wready;
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assign emwr_rd_en = ( emwr_access & ~awvalid_b & ~wvalid_b);
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// generate write-address signals
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always @( posedge m_axi_aclk )
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if(~m_axi_aresetn)
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begin
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m_axi_awvalid <= 1'b0;
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m_axi_awaddr[31:0] <= 32'd0;
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m_axi_awlen[7:0] <= 8'd0;
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m_axi_awsize[2:0] <= 3'd0;
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awvalid_b <= 1'b0;
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awaddr_b[31:0] <= 32'd0;
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awlen_b[7:0] <= 8'd0;
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awsize_b[2:0] <= 3'd0;
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end
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else
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begin
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if( ~m_axi_awvalid | aw_go )
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begin
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if( awvalid_b )
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begin
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m_axi_awvalid <= 1'b1;
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m_axi_awaddr[31:0] <= awaddr_b[31:0];
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m_axi_awlen[7:0] <= awlen_b[7:0];
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m_axi_awsize[2:0] <= awsize_b[2:0];
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end
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else
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begin
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m_axi_awvalid <= emwr_rd_en;
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m_axi_awaddr[31:0] <= emwr_dstaddr[31:0];
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m_axi_awlen[7:0] <= 8'b0;
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m_axi_awsize[2:0] <= { 1'b0, emwr_datamode[1:0]};
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end
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end
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if( emwr_rd_en & m_axi_awvalid & ~aw_go )
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awvalid_b <= 1'b1;
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else if( aw_go )
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awvalid_b <= 1'b0;
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//Pipeline stage
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if( emwr_rd_en )
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begin
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awaddr_b[31:0] <= emwr_dstaddr[31:0];
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awlen_b[7:0] <= 8'b0;
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awsize_b[2:0] <= { 1'b0, emwr_datamode[1:0] };
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end
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end // else: !if(~m_axi_aresetn)
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//--------------------
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//write alignment circuit
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//--------------------
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always @*
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case( emwr_datamode[1:0] )
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2'd0: wdata_aligned[63:0] = { 8{emwr_data[7:0]}};
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2'd1: wdata_aligned[63:0] = { 4{emwr_data[15:0]}};
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2'd2: wdata_aligned[63:0] = { 2{emwr_data[31:0]}};
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default: wdata_aligned[63:0] = { emwr_srcaddr[31:0], emwr_data[31:0]};
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endcase
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//TODO: Simplify logic below!!!!!
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//Should include separate fields for address/data/datamode!!!!
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always @*
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begin
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case(emwr_datamode[1:0])
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2'd0: // byte
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case(emwr_dstaddr[2:0])
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3'd0: wstrb_aligned[7:0] = 8'h01;
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3'd1: wstrb_aligned[7:0] = 8'h02;
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3'd2: wstrb_aligned[7:0] = 8'h04;
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3'd3: wstrb_aligned[7:0] = 8'h08;
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3'd4: wstrb_aligned[7:0] = 8'h10;
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3'd5: wstrb_aligned[7:0] = 8'h20;
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3'd6: wstrb_aligned[7:0] = 8'h40;
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default: wstrb_aligned[7:0] = 8'h80;
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endcase
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2'd1: // 16b hword
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case(emwr_dstaddr[2:1])
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2'd0: wstrb_aligned[7:0] = 8'h03;
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2'd1: wstrb_aligned[7:0] = 8'h0c;
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2'd2: wstrb_aligned[7:0] = 8'h30;
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default: wstrb_aligned[7:0] = 8'hc0;
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endcase
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2'd2: // 32b word
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if(emwr_dstaddr[2])
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wstrb_aligned[7:0] = 8'hf0;
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else
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wstrb_aligned[7:0] = 8'h0f;
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2'd3:
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wstrb_aligned[7:0] = 8'hff;
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endcase // case (emwr_datamode[1:0])
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end // always @ *
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// generate the write-data signals
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always @ (posedge m_axi_aclk )
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if(~m_axi_aresetn)
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begin
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m_axi_wvalid <= 1'b0;
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m_axi_wdata[63:0] <= 64'b0;
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m_axi_wstrb[7:0] <= 8'b0;
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m_axi_wlast <= 1'b1; // todo: no bursts for now?
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wvalid_b <= 1'b0;
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wdata_b[63:0] <= 64'b0;
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wstrb_b[7:0] <= 8'b0;
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end
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else
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begin
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if( ~m_axi_wvalid | w_go )
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begin
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if( wvalid_b )
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begin
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m_axi_wvalid <= 1'b1;
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m_axi_wdata[63:0] <= wdata_b[63:0];
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m_axi_wstrb[7:0] <= wstrb_b[7:0];
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end
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else
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begin
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m_axi_wvalid <= emwr_rd_en;//todo
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m_axi_wdata[63:0] <= wdata_aligned[63:0];
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m_axi_wstrb[7:0] <= wstrb_aligned[7:0];
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end
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end // if ( ~axi_wvalid | w_go )
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if( emwr_rd_en & m_axi_wvalid & ~w_go )
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wvalid_b <= 1'b1;
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else if( w_go )
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wvalid_b <= 1'b0;
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if( emwr_rd_en )
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begin
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wdata_b[63:0] <= wdata_aligned[63:0];
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wstrb_b[7:0] <= wstrb_aligned[7:0];
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end
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end // else: !if(~m_axi_aresetn)
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//----------------------------
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// read handler
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// elink read requests generate a transaction on the ar channel,
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// buffer the src info to generate an elink write when the
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// read data comes back.
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//----------------------------
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//TODO: Can we improve this??
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assign readinfo_in[47:0] =
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{
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7'b0,
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emrq_srcaddr[31:0],//40:9
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emrq_dstaddr[2:0], //8:6
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emrq_ctrlmode[3:0], //5:2
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emrq_datamode[1:0]
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};
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fifo_sync
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#(
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// parameters
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.AW (5),
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.DW (48))
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fifo_readinfo_i
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(
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// outputs
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.rd_data (readinfo_out[47:0]),
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.rd_empty (),
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.wr_full (readinfo_full),
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// inputs
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.clk (m_axi_aclk),
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.reset (~m_axi_aresetn),
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.wr_data (readinfo_in[47:0]),
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.wr_en (emrq_rd_en),
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.rd_en (readinfo_rden));
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assign emrr_datamode[1:0] = readinfo_out[1:0];
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assign emrr_ctrlmode[3:0] = readinfo_out[5:2];
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assign emrr_dstaddr[31:0] = readinfo_out[40:9];
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//----------------------------
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// read address channel
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//----------------------------
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assign m_axi_araddr[31:0] = emrq_dstaddr[31:0];
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assign m_axi_arsize[2:0] = {1'b0, emrq_datamode[1:0]};
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assign m_axi_arlen[7:0] = 8'd0;
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assign m_axi_arvalid = emrq_access & ~readinfo_full;
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assign emrq_rd_en = m_axi_arvalid & m_axi_arready;
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//--------------------------------
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// read data (and response) channel
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//--------------------------------
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assign m_axi_rready = ~emrr_progfull;
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assign readinfo_rden = ~emrr_progfull & m_axi_rvalid;
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assign emrr_write = 1'b1;
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always @( posedge m_axi_aclk )
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if( ~m_axi_aresetn )
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begin
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emrr_data[31:0] <= 32'b0;
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emrr_srcaddr[31:0] <= 32'b0;
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emrr_access_reg <= 1'b0;
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emrr_access <= 1'b0;
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end
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else
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begin
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emrr_access_reg <= m_axi_rready & m_axi_rvalid;
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emrr_access <= emrr_access_reg;//added pipeline stage for data
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emrr_srcaddr[31:0] <= m_axi_rdata[63:32];
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// steer read data according to size & host address lsbs
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//all data needs to be right aligned
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//(this is due to the Epiphany right aligning all words)
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case(readinfo_out[1:0])//datamode
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2'd0: // byte read
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case(readinfo_out[8:6])
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3'd0: emrr_data[7:0] <= m_axi_rdata[7:0];
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3'd1: emrr_data[7:0] <= m_axi_rdata[15:8];
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3'd2: emrr_data[7:0] <= m_axi_rdata[23:16];
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3'd3: emrr_data[7:0] <= m_axi_rdata[31:24];
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3'd4: emrr_data[7:0] <= m_axi_rdata[39:32];
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3'd5: emrr_data[7:0] <= m_axi_rdata[47:40];
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3'd6: emrr_data[7:0] <= m_axi_rdata[55:48];
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default: emrr_data[7:0] <= m_axi_rdata[63:56];
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endcase
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2'd1: // 16b hword
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case( readinfo_out[8:7] )
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2'd0: emrr_data[15:0] <= m_axi_rdata[15:0];
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2'd1: emrr_data[15:0] <= m_axi_rdata[31:16];
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2'd2: emrr_data[15:0] <= m_axi_rdata[47:32];
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default: emrr_data[15:0] <= m_axi_rdata[63:48];
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endcase
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2'd2: // 32b word
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if( readinfo_out[8] )
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emrr_data[31:0] <= m_axi_rdata[63:32];
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else
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emrr_data[31:0] <= m_axi_rdata[31:0];
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// 64b word already defined by defaults above
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2'd3: begin // 64b dword
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emrr_data[31:0] <= m_axi_rdata[31:0];
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end
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endcase
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end // else: !if( ~m_axi_aresetn )
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endmodule
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/*
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copyright (c) 2014 adapteva, inc.
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contributed by fred huettig <fred@adapteva.com>
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contributed by andreas olofsson <andreas@adapteva.com>
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this program is free software: you can redistribute it and/or modify
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it under the terms of the gnu general public license as published by
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the free software foundation, either version 3 of the license, or
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(at your option) any later version.
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this program is distributed in the hope that it will be useful,
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but without any warranty; without even the implied warranty of
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merchantability or fitness for a particular purpose. see the
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gnu general public license for more details.
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you should have received a copy of the gnu general public license
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along with this program (see the file copying). if not, see
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<http://www.gnu.org/licenses/>.
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*/
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