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280 lines
9.2 KiB
Verilog
280 lines
9.2 KiB
Verilog
module erx_core (/*AUTOARG*/
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// Outputs
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rx_rd_wait, rx_wr_wait, idelay_value, load_taps, rxrd_access,
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rxrd_packet, rxrr_access, rxrr_packet, rxwr_access, rxwr_packet,
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erx_cfg_wait, mailbox_irq,
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// Inputs
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nreset, clk, rx_packet, rx_access, rx_burst, rxrd_wait, rxrr_wait,
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rxwr_wait, erx_cfg_access, erx_cfg_packet
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h999;
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parameter TARGET = "GENERIC";
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//clock and reset
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input nreset; //synced to clk
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input clk;
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//IO Interface
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input [PW-1:0] rx_packet;
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input rx_access;
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input rx_burst;
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output rx_rd_wait;
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output rx_wr_wait;
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output [44:0] idelay_value;
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output load_taps;
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//FIFO Access
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//register interface
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input erx_cfg_access;
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input [PW-1:0] erx_cfg_packet;
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output erx_cfg_wait;
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//mailbox outputs
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output mailbox_irq;
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/*AUTOINPUT*/
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire dma_access; // From erx_cfg of erx_cfg.v
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wire ecfg_access; // From erx_cfg of erx_cfg.v
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wire [PW-1:0] ecfg_packet; // From erx_cfg of erx_cfg.v
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wire edma_wait; // From erx_arbiter of erx_arbiter.v
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wire emesh_remap_access; // From erx_remap of erx_remap.v
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wire [PW-1:0] emesh_remap_packet; // From erx_remap of erx_remap.v
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wire emmu_access; // From erx_mmu of emmu.v
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wire [PW-1:0] emmu_packet; // From erx_mmu of emmu.v
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wire erx_access; // From erx_protocol of erx_protocol.v
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wire [PW-1:0] erx_packet; // From erx_protocol of erx_protocol.v
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wire mailbox_access; // From erx_cfg of erx_cfg.v
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wire mailbox_irq_en; // From erx_cfg of erx_cfg.v
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wire [31:0] mailbox_rdata; // From erx_mailbox of emailbox.v
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wire mailbox_wait; // From erx_mailbox of emailbox.v
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wire mmu_access; // From erx_cfg of erx_cfg.v
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wire mmu_enable; // From erx_cfg of erx_cfg.v
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wire [31:0] remap_base; // From erx_cfg of erx_cfg.v
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wire [1:0] remap_mode; // From erx_cfg of erx_cfg.v
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wire [11:0] remap_pattern; // From erx_cfg of erx_cfg.v
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wire [11:0] remap_sel; // From erx_cfg of erx_cfg.v
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wire test_mode; // From erx_cfg of erx_cfg.v
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// End of automatics
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//regs
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wire [8:0] gpio_datain;
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wire [15:0] rx_status;
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wire rxwr_full;
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wire rxrr_full;
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wire rxrd_full;
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wire rxrd_empty;
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wire rxwr_empty;
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wire rxrr_empty;
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wire [103:0] edma_packet;
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/**************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/**************************************************************/
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erx_protocol #(.ID(ID))
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erx_protocol (/*AUTOINST*/
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// Outputs
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.erx_access (erx_access),
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.erx_packet (erx_packet[PW-1:0]),
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// Inputs
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.clk (clk),
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.test_mode (test_mode),
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.rx_packet (rx_packet[PW-1:0]),
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.rx_burst (rx_burst),
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.rx_access (rx_access));
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/**************************************************************/
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/*ADDRESS REMPAPPING */
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/**************************************************************/
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/*erx_remap AUTO_TEMPLATE (
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.emesh_\(.*\)_out (emesh_remap_\1[]),
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//Inputs
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.emesh_access_in (erx_access),
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.emesh_\(.*\)_in (erx_\1[]),
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.mmu_en (ecfg_rx_mmu_enable),
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.emesh_packet_hi_out (),
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);
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*/
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erx_remap #(.ID(ID))
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erx_remap (/*AUTOINST*/
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// Outputs
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.emesh_access_out (emesh_remap_access), // Templated
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.emesh_packet_out (emesh_remap_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.emesh_access_in (erx_access), // Templated
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.emesh_packet_in (erx_packet[PW-1:0]), // Templated
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.remap_mode (remap_mode[1:0]),
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.remap_sel (remap_sel[11:0]),
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.remap_pattern (remap_pattern[11:0]),
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.remap_base (remap_base[31:0]));
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/************************************************************/
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/*ELINK MEMORY MANAGEMENT UNIT */
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/************************************************************/
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/*emmu AUTO_TEMPLATE (.reg_access (mmu_access),
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.reg_packet (erx_cfg_packet[PW-1:0]),
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.emesh_\(.*\)_out (emmu_\1[]),
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.emesh_\(.*\)_in (emesh_remap_\1[]),
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.mmu_en (mmu_enable),
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.\(.*\)_clk (clk),
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);
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*/
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emmu erx_mmu (.emesh_wait_in (1'b0),
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.reg_rdata (),
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/*AUTOINST*/
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// Outputs
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.emesh_access_out (emmu_access), // Templated
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.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
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// Inputs
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.nreset (nreset),
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.mmu_en (mmu_enable), // Templated
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.wr_clk (clk), // Templated
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.reg_access (mmu_access), // Templated
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.reg_packet (erx_cfg_packet[PW-1:0]), // Templated
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.rd_clk (clk), // Templated
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.emesh_access_in (emesh_remap_access), // Templated
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.emesh_packet_in (emesh_remap_packet[PW-1:0])); // Templated
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/************************************************************/
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/*EMAILBOX */
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/************************************************************/
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/*emailbox AUTO_TEMPLATE (
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.mi_en (mi_cfg_en),
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.mi_dout (mi_mailbox_dout[]),
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.\(.*\)_clk (clk),
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.emesh_\(.*\) (emmu_\1[]),
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.reg_access (mailbox_access),
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.reg_rdata (mailbox_rdata[31:0]),
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.reg_packet (erx_cfg_packet[PW-1:0]),
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);
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*/
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emailbox #(.ID(ID), .TARGET(TARGET))
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erx_mailbox(
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/*AUTOINST*/
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// Outputs
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.reg_rdata (mailbox_rdata[31:0]), // Templated
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.mailbox_irq (mailbox_irq),
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.mailbox_wait (mailbox_wait),
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// Inputs
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.nreset (nreset),
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.wr_clk (clk), // Templated
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.rd_clk (clk), // Templated
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.emesh_access (emmu_access), // Templated
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.emesh_packet (emmu_packet[PW-1:0]), // Templated
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.reg_access (mailbox_access), // Templated
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.reg_packet (erx_cfg_packet[PW-1:0]), // Templated
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.mailbox_irq_en (mailbox_irq_en));
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/************************************************************/
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/* ERX CONFIGURATION */
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/************************************************************/
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erx_cfg erx_cfg (.gpio_datain (9'b0),
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.rx_status ({11'b0,
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rx_rd_wait,
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rx_wr_wait,
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rxrr_wait,
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rxrd_wait,
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rxwr_wait
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}
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),
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.edma_rdata (32'b0),
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/*AUTOINST*/
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// Outputs
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.mmu_access (mmu_access),
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.dma_access (dma_access),
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.mailbox_access (mailbox_access),
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.ecfg_access (ecfg_access),
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.ecfg_packet (ecfg_packet[PW-1:0]),
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.mmu_enable (mmu_enable),
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.remap_mode (remap_mode[1:0]),
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.remap_base (remap_base[31:0]),
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.remap_pattern (remap_pattern[11:0]),
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.remap_sel (remap_sel[11:0]),
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.idelay_value (idelay_value[44:0]),
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.load_taps (load_taps),
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.test_mode (test_mode),
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.mailbox_irq_en (mailbox_irq_en),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.erx_cfg_access (erx_cfg_access),
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.erx_cfg_packet (erx_cfg_packet[PW-1:0]),
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.mailbox_rdata (mailbox_rdata[31:0]),
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.erx_access (erx_access),
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.erx_packet (erx_packet[PW-1:0]));
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/************************************************************/
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/*ELINK RECEIVE DISTRIBUTOR ("DEMUX") */
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/*(figures out who RX transaction belongs to) */
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/************************************************************/
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/*erx_arbiter AUTO_TEMPLATE (
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//Inputs
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.mmu_en (ecfg_rx_mmu_enable),
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.ecfg_wait (erx_cfg_wait),
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.erx_access (emmu_access),
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.erx_packet (emmu_packet[PW-1:0]),
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)
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*/
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erx_arbiter #(.ID(ID))
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erx_arbiter (.edma_access (1'b0),
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.edma_packet ({(PW){1'b0}}),
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/*AUTOINST*/
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// Outputs
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.rx_rd_wait (rx_rd_wait),
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.rx_wr_wait (rx_wr_wait),
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.edma_wait (edma_wait),
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.ecfg_wait (erx_cfg_wait), // Templated
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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// Inputs
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.erx_access (emmu_access), // Templated
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.erx_packet (emmu_packet[PW-1:0]), // Templated
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.mailbox_wait (mailbox_wait),
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.ecfg_access (ecfg_access),
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.ecfg_packet (ecfg_packet[PW-1:0]),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.rxrr_wait (rxrr_wait));
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endmodule // erx_core
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
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// End:
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