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https://github.com/aolofsson/oh.git
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51c8ae600d
-Solved a speed path in synchronizing the wait signal, had to use the first edge signal fo the IO and the lclk_div4 for the core logic. It seems that the FPGA has a really hard time mixing clock domains, the routing delay between domains explodes -Put in some special case logic for edge cases, like when there is a wait coming in from the IO and there is a wait from the IO. In that case, the packet gets sampled by the IO and not by the current logic. -This needs to be cleaned up eventually, not clean enough but it's good enough for now.
158 lines
4.5 KiB
Verilog
158 lines
4.5 KiB
Verilog
`include "elink_regmap.v"
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module etx_protocol (/*AUTOARG*/
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// Outputs
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etx_rd_wait, etx_wr_wait, tx_packet, tx_access, tx_burst,
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// Inputs
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nreset, clk, etx_access, etx_packet, tx_enable, gpio_data,
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gpio_enable, tx_rd_wait, tx_wr_wait
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);
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parameter PW = 104;
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parameter AW = 32;
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parameter DW = 32;
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parameter ID = 12'h000;
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//Clock/reset
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input nreset;
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input clk;
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//System side
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input etx_access;
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input [PW-1:0] etx_packet;
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//Pushback signals
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output etx_rd_wait;
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output etx_wr_wait;
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//Enble transmit
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input tx_enable; //transmit enable
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input [8:0] gpio_data; //TODO
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input gpio_enable; //TODO
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//Interface to IO
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output [PW-1:0] tx_packet;
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output tx_access;
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output tx_burst;
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input tx_rd_wait; // The wait signals are passed through
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input tx_wr_wait; // to the emesh interfaces
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//###################################################################
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//# Local regs & wires
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//###################################################################
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reg tx_access;
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reg [PW-1:0] tx_packet;
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reg tx_io_wait;
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reg tx_burst;
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wire etx_write;
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wire [1:0] etx_datamode;
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wire [3:0] etx_ctrlmode;
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wire [AW-1:0] etx_dstaddr;
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wire [DW-1:0] etx_data;
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wire last_write;
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wire [1:0] last_datamode;
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wire [3:0] last_ctrlmode;
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wire [AW-1:0] last_dstaddr;
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wire burst_match;
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wire burst_type_match;
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wire [31:0] burst_addr;
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wire burst_addr_match;
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wire burst_in;
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//##############################################################
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//# Packet Pipeline
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//##############################################################
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packet2emesh p2m0 (
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.write_out (etx_write),
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.datamode_out (etx_datamode[1:0]),
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.ctrlmode_out (etx_ctrlmode[3:0]),
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.dstaddr_out (etx_dstaddr[31:0]),
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.data_out (),
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.srcaddr_out (),
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.packet_in (etx_packet[PW-1:0]));//input
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//Creates a one cycle wait whenever there is no burst
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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tx_io_wait <= 1'b0;
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else if (tx_rd_wait | tx_wr_wait)
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tx_io_wait <= 1'b0;
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else
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tx_io_wait <= (~tx_io_wait & etx_access & ~tx_burst_in);
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//Hold transaction while waiting
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//This transaction should be flushed out on wait????
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always @ (posedge clk)
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if(!nreset)
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begin
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tx_packet[PW-1:0] <= 'b0;
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tx_access <= 1'b0;
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end
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else if(~(etx_wr_wait | etx_rd_wait))
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begin
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tx_packet[PW-1:0] <= etx_packet[PW-1:0];
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tx_access <= tx_enable & etx_access;
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end
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//#############################
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//# Burst Detection
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//#############################
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packet2emesh p2m1 (
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.write_out (last_write),
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.datamode_out (last_datamode[1:0]),
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.ctrlmode_out (last_ctrlmode[3:0]),
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.dstaddr_out (last_dstaddr[31:0]),
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.data_out (),
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.srcaddr_out (),
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.packet_in (tx_packet[PW-1:0]));//input
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assign burst_addr[31:0] = (last_dstaddr[31:0] + 32'h8);
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assign burst_addr_match = (burst_addr[31:0] == etx_dstaddr[31:0]);
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assign burst_type_match = {last_ctrlmode[3:0],last_datamode[1:0],last_write}
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==
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{etx_ctrlmode[3:0],etx_datamode[1:0], etx_write};
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assign tx_burst_in = tx_access & //avoid garbage
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~tx_wr_wait_reg & //clear on wait
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etx_write & //write
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(etx_datamode[1:0]==2'b11) & //double only
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burst_type_match & //same types
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burst_addr_match; //inc by 8
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reg tx_wr_wait_reg;
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reg tx_rd_wait_reg;
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reg tx_io_wait_reg;
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//sample to align up witth tx_access
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always @ (posedge clk)
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begin
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tx_burst <= tx_burst_in;
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tx_wr_wait_reg <= tx_wr_wait;
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tx_rd_wait_reg <= tx_rd_wait;
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tx_io_wait_reg <= tx_io_wait;
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end
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assign special_sample = tx_io_wait_reg &
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(tx_wr_wait | tx_rd_wait) &
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~(tx_wr_wait_reg | tx_rd_wait_reg)
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;
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//#############################
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//# Wait propagation circuit
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//#############################
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assign etx_wr_wait = (tx_wr_wait | tx_io_wait) & ~special_sample;
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assign etx_rd_wait = (tx_rd_wait | tx_io_wait) & ~special_sample;
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endmodule // etx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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