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200 lines
7.1 KiB
Verilog
200 lines
7.1 KiB
Verilog
`include "mio_regmap.vh"
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module mio_regs (/*AUTOARG*/
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// Outputs
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wait_out, access_out, packet_out, tx_en, rx_en, ddr_mode, emode,
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amode, dmode, datasize, lsbfirst, ctrlmode, dstaddr, clkdiv,
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clkphase0, clkphase1,
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// Inputs
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clk, nreset, access_in, packet_in, wait_in, addrincr, tx_full,
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tx_prog_full, tx_empty, rx_full, rx_prog_full, rx_empty
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);
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// parameters
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parameter N = 8; // number of I/O pins
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parameter AW = 32; // address width
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localparam PW = 2*AW+40; // packet width
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parameter DEF_CFG = 0; // default enable value (1 is on)
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parameter DEF_CLK = 0; // default CLKDIV value (divide by 8)
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localparam DEF_RISE0 = 0; // 0 degrees
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localparam DEF_FALL0 = ((DEF_CLK+8'd1)>>8'd1); // 180 degrees
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localparam DEF_RISE1 = ((DEF_CLK+8'd1)>>8'd2); // 90 degrees
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localparam DEF_FALL1 = ((DEF_CLK+8'd1)>>8'd2)+
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((DEF_CLK+8'd1)>>8'd1); // 270 degrees
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// clk,reset
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input clk;
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input nreset;
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// packet interface
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input access_in; // incoming access
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input [PW-1:0] packet_in; // incoming packet
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output wait_out;
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output access_out; // outgoing read packet
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output [PW-1:0] packet_out; // outgoing read packet
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input wait_in;
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// config
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output tx_en; // enable tx
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output rx_en; // enable rx
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output ddr_mode; // ddr mode for mio
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output emode; // epiphany packet mode
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output amode; // mio packet mode
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output dmode; // mio packet mode
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output [7:0] datasize; // mio datasize
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output lsbfirst; // lsb shift first
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output [4:0] ctrlmode; // emode ctrlmode
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input [3:0] addrincr; // address update in amode
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//address
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output [AW-1:0] dstaddr; // destination address for RX dmode
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// clock
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output [7:0] clkdiv; // mio clk clock setting
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output [15:0] clkphase0; // [7:0]=rising,[15:8]=falling
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output [15:0] clkphase1; // [7:0]=rising,[15:8]=falling
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// status
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input tx_full; //tx fifo is full (should not happen!)
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input tx_prog_full; //tx fifo is nearing full
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input tx_empty; //tx fifo is empty
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input rx_full; //rx fifo is full (should not happen!)
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input rx_prog_full; //rx fifo is nearing full
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input rx_empty; //rx fifo is empty
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//######################################################################
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//# BODY
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//######################################################################
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] data_in; // From p2e of packet2emesh.v
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wire [1:0] datamode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
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wire write_in; // From p2e of packet2emesh.v
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// End of automatics
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//regs
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reg [18:0] config_reg;
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reg [7:0] status_reg;
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wire [7:0] status_in;
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reg [31:0] clkdiv_reg;
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reg [63:0] addr_reg;
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reg [31:0] clkphase_reg;
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//#####################################
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//# DECODE
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//#####################################
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packet2emesh #(.AW(AW))
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p2e (/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]),
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// Inputs
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.packet_in (packet_in[PW-1:0]));
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assign reg_write = write_in & access_in;
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assign config_write = reg_write & (dstaddr_in[5:2]==`MIO_CONFIG);
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assign status_write = reg_write & (dstaddr_in[5:2]==`MIO_STATUS);
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assign clkdiv_write = reg_write & (dstaddr_in[5:2]==`MIO_CLKDIV);
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assign clkphase_write = reg_write & (dstaddr_in[5:2]==`MIO_CLKPHASE);
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assign idelay_write = reg_write & (dstaddr_in[5:2]==`MIO_IDELAY);
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assign odelay_write = reg_write & (dstaddr_in[5:2]==`MIO_ODELAY);
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assign addr0_write = reg_write & (dstaddr_in[5:2]==`MIO_ADDR0);
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assign addr1_write = reg_write & (dstaddr_in[5:2]==`MIO_ADDR1);
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//################################
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//# CONFIG
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//################################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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begin
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config_reg[18:0] <= DEF_CFG;
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end
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else if(config_write)
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config_reg[18:0] <= data_in[18:0];
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assign tx_en = ~config_reg[0]; // tx disable
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assign rx_en = ~config_reg[1]; // rx disable
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assign emode = config_reg[3:2]==2'b00; // emesh packets
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assign dmode = config_reg[3:2]==2'b01; // pure data mode (streaming)
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assign amode = config_reg[3:2]==2'b10; // auto address mode
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assign datasize[7:0] = config_reg[11:4]; // number of flits per packet
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assign ddr_mode = config_reg[12]; // dual data rate mode
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assign lsbfirst = config_reg[13]; // lsb-first transmit
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assign ctrlmode[4:0] = config_reg[18:14]; // amode ctrlmode
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//###############################
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//# STATUS
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//################################
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assign status_in[7:0] = {2'b0, //7:6
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tx_full, //5
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tx_prog_full,//4
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tx_empty, //3
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rx_full, //2
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rx_prog_full,//1
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rx_empty //0
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};
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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status_reg[7:0] <= 'b0;
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else if(status_write)
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status_reg[7:0] <= data_in[7:0];
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else
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status_reg[7:0] <= {(status_reg[15:8] | status_in[7:0]), // sticky bits
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status_in[7:0]}; // immediate bits
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//###############################
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//# CLKDIV
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//################################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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clkdiv_reg[7:0] <= DEF_CLK;
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else if(clkdiv_write)
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clkdiv_reg[7:0] <= data_in[7:0];
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assign clkdiv[7:0] = clkdiv_reg[7:0];
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//###############################
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//# CLKPHASE
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//################################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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begin
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clkphase_reg[7:0] <= DEF_RISE0;
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clkphase_reg[15:8] <= DEF_FALL0;
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clkphase_reg[23:16] <= DEF_RISE1;
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clkphase_reg[31:24] <= DEF_FALL1;
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end
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else if(clkphase_write)
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clkphase_reg[31:0] <= data_in[31:0];
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assign clkphase0[15:0] = clkphase_reg[15:0];
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assign clkphase1[15:0] = clkphase_reg[31:16];
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//###############################
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//# RX DESTINATION ADDR ("AMODE")
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//################################
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always @ (posedge clk)
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if(addr0_write)
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addr_reg[31:0] <= data_in[31:0];
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else if(addr1_write)
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addr_reg[63:32] <= data_in[31:0];
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else
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addr_reg[63:0] <= addr_reg[63:0] + addrincr[3:0];
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assign dstaddr[AW-1:0] = addr_reg[AW-1:0];
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endmodule // io_cfg
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// Local Variables:
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// verilog-library-directories:("." "../../../oh/emesh/hdl" "../../../oh/common/hdl")
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// End:
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