mirror of
https://github.com/aolofsson/oh.git
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d275406aa6
- holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
291 lines
10 KiB
Verilog
291 lines
10 KiB
Verilog
module elink(/*AUTOARG*/
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// Outputs
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rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n, chipid, cclk_p, cclk_n, chip_resetb, mailbox_not_empty,
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mailbox_full, timeout, rxwr_access, rxwr_packet, rxrd_access,
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rxrd_packet, rxrr_access, rxrr_packet, txwr_wait, txrd_wait,
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txrr_wait,
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// Inputs
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sys_reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
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txi_rd_wait_p, txi_rd_wait_n, rxwr_wait, rxrd_wait, rxrr_wait,
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txwr_access, txwr_packet, txrd_access, txrd_packet, txrr_access,
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txrr_packet
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);
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parameter AW = 32; //native address width
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parameter DW = 32; //native data width
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parameter PW = 104; //packet width
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parameter ID = 12'h810; //epiphany ID for elink (ie addr[31:20])
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parameter IOSTD_ELINK = "LVDS_25";
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parameter ETYPE = 1;
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/****************************/
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/*CLOCK AND RESET */
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/****************************/
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input sys_reset; // reset for
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input sys_clk; // a single system clock for master/slave FIFOs
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/********************************/
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/*ELINK RECEIVER */
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/********************************/
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input rxi_lclk_p, rxi_lclk_n; // rx clock input
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input rxi_frame_p, rxi_frame_n; // rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; // rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
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/********************************/
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/*ELINK TRANSMITTER */
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/********************************/
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output txo_lclk_p, txo_lclk_n; // tx clock output
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output txo_frame_p, txo_frame_n; // tx frame signal
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output [7:0] txo_data_p, txo_data_n; // tx data
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input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback input
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input txi_rd_wait_p,txi_rd_wait_n; // tx read pushback input
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/*************************************/
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/*EPIPHANY MISC INTERFACE (I/O PINS) */
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/*************************************/
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output [11:0] chipid; // chip id strap pins for epiphany
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output cclk_p, cclk_n; //chip clock
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output chip_resetb; // From etx of etx.v
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/*****************************/
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/*MAILBOX INTERRUPTS */
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/*****************************/
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output mailbox_not_empty;
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output mailbox_full;
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/*****************************/
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/* */
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/*****************************/
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output timeout;
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/*****************************/
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/*SYSTEM SIDE INTERFACE */
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/*****************************/
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//Master Write (from RX)
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//Master Read Request (from RX)
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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//Slave Read Response (from RX)
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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//Slave Write (to TX)
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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//Slave Read Request (to TX)
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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//Master Read Response (to TX)
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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/*#############################################*/
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/* END OF BLOCK INTERFACE */
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/*#############################################*/
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/*AUTOINPUT*/
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//wire
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wire erx_cfg_access; // To erx of erx.v
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wire [PW-1:0] erx_cfg_packet; // To erx of erx.v
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wire etx_cfg_wait; // To etx of etx.v
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wire [31:0] mi_rd_data;
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wire [31:0] mi_dout_ecfg;
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wire [31:0] mi_dout_embox;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire erx_cfg_wait; // From erx of erx.v
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wire erx_reset; // From erx of erx.v
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wire erx_soft_reset; // From ecfg_elink of ecfg_elink.v
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wire etx_cfg_access; // From etx of etx.v
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wire [PW-1:0] etx_cfg_packet; // From etx of etx.v
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wire etx_reset; // From etx of etx.v
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wire etx_soft_reset; // From ecfg_elink of ecfg_elink.v
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wire rx_lclk_div4; // From erx of erx.v
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wire tx_active; // From etx of etx.v
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wire tx_lclk_div4; // From etx of etx.v
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wire txwr_gated_access; // From ecfg_elink of ecfg_elink.v
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// End of automatics
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/***********************************************************/
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/*CLOCK AND RESET CONFIG */
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/***********************************************************/
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defparam ecfg_elink.ID=ID;
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ecfg_elink ecfg_elink (.clk (sys_clk),
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.por_reset (sys_reset),
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.clk_config (),
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/*AUTOINST*/
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// Outputs
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.txwr_gated_access (txwr_gated_access),
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.etx_soft_reset (etx_soft_reset),
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.erx_soft_reset (erx_soft_reset),
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.chipid (chipid[11:0]),
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// Inputs
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]));
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/***********************************************************/
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/*RECEIVER */
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/***********************************************************/
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/*erx AUTO_TEMPLATE (
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.mi_dout (mi_rx_dout[]),
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.soft_reset (erx_soft_reset),
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);
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*/
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defparam erx.ID = ID;
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defparam erx.IOSTD_ELINK = IOSTD_ELINK;
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defparam erx.ETYPE = ETYPE;
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erx erx(
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/*AUTOINST*/
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// Outputs
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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.rxo_rd_wait_n (rxo_rd_wait_n),
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.erx_cfg_wait (erx_cfg_wait),
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.rx_lclk_div4 (rx_lclk_div4),
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.erx_reset (erx_reset),
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.timeout (timeout),
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.mailbox_full (mailbox_full),
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.mailbox_not_empty (mailbox_not_empty),
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// Inputs
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.soft_reset (erx_soft_reset), // Templated
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.sys_reset (sys_reset),
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.sys_clk (sys_clk),
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.tx_active (tx_active),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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.rxi_frame_n (rxi_frame_n),
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.rxi_data_p (rxi_data_p[7:0]),
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.rxi_data_n (rxi_data_n[7:0]),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.rxrr_wait (rxrr_wait),
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.erx_cfg_access (erx_cfg_access),
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.erx_cfg_packet (erx_cfg_packet[PW-1:0]));
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/***********************************************************/
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/*TRANSMITTER */
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/***********************************************************/
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/*etx AUTO_TEMPLATE (.mi_dout (mi_tx_dout[]),
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.emwr_\(.*\) (esaxi_emwr_\1[]),
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.emrq_\(.*\) (esaxi_emrq_\1[]),
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.emrr_\(.*\) (emaxi_emrr_\1[]),
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.soft_reset (etx_soft_reset),
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.txwr_access (txwr_gated_access),
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);
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*/
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defparam etx.ID = ID;
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defparam etx.IOSTD_ELINK = IOSTD_ELINK;
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defparam etx.ETYPE = ETYPE;
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etx etx(
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/*AUTOINST*/
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// Outputs
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.tx_active (tx_active),
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.txo_lclk_p (txo_lclk_p),
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.txo_lclk_n (txo_lclk_n),
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.txo_frame_p (txo_frame_p),
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.chip_resetb (chip_resetb),
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.txrd_wait (txrd_wait),
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.txwr_wait (txwr_wait),
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.txrr_wait (txrr_wait),
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.etx_cfg_access (etx_cfg_access),
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.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
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.etx_reset (etx_reset),
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.tx_lclk_div4 (tx_lclk_div4),
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// Inputs
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.sys_reset (sys_reset),
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.soft_reset (etx_soft_reset), // Templated
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.sys_clk (sys_clk),
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.txi_wr_wait_p (txi_wr_wait_p),
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.txi_wr_wait_n (txi_wr_wait_n),
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.txi_rd_wait_p (txi_rd_wait_p),
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.txi_rd_wait_n (txi_rd_wait_n),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txwr_access (txwr_gated_access), // Templated
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]),
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.etx_cfg_wait (etx_cfg_wait));
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/***********************************************************/
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/*TX-->RX REGISTER INTERFACE CONNECTION */
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/***********************************************************/
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defparam ecfg_cdc.DW=104;
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defparam ecfg_cdc.DEPTH=32;
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fifo_cdc ecfg_cdc (// Outputs
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.wait_out (etx_cfg_wait),
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.access_out (erx_cfg_access),
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.packet_out (erx_cfg_packet[PW-1:0]),
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// Inputs
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.clk_in (tx_lclk_div4),
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.reset_in (etx_reset),
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.access_in (etx_cfg_access),
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.packet_in (etx_cfg_packet[PW-1:0]),
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.clk_out (rx_lclk_div4),
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.reset_out (erx_reset),
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.wait_in (erx_cfg_wait)
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);
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../erx/hdl" "../../etx/hdl" "../../memory/hdl")
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// End:
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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