mirror of
https://github.com/aolofsson/oh.git
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d275406aa6
- holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
237 lines
8.8 KiB
Verilog
237 lines
8.8 KiB
Verilog
module etx(/*AUTOARG*/
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// Outputs
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tx_active, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
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txo_data_p, txo_data_n, cclk_p, cclk_n, chip_resetb, txrd_wait,
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txwr_wait, txrr_wait, etx_cfg_access, etx_cfg_packet, etx_reset,
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tx_lclk_div4,
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// Inputs
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sys_reset, soft_reset, sys_clk, txi_wr_wait_p, txi_wr_wait_n,
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txi_rd_wait_p, txi_rd_wait_n, txrd_access, txrd_packet,
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txwr_access, txwr_packet, txrr_access, txrr_packet, etx_cfg_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h000;
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parameter IOSTD_ELINK = "LVDS_25";
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parameter ETYPE = 1;
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//Reset and clocks
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input sys_reset; // reset for fifos
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input soft_reset; // software controlled reset
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//Clocks
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input sys_clk; // clock for fifos
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//TX boot done
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output tx_active; // tx ready to transmit
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//Transmit signals for IO
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output txo_lclk_p, txo_lclk_n; // tx clock output
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output txo_frame_p, txo_frame_n; // tx frame signal
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output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
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input txi_wr_wait_p,txi_wr_wait_n; // tx async write pushback
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input txi_rd_wait_p, txi_rd_wait_n; // tx async read pushback
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//Epiphany Chip Signals
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output cclk_p,cclk_n;
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output chip_resetb;
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//Read Request Channel Input
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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//Write Channel Input
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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//Read Response Channel Input
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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//Configuration Interface (for ERX)
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output etx_cfg_access;
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output [PW-1:0] etx_cfg_packet;
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output etx_reset;
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output tx_lclk_div4;
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input etx_cfg_wait;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire tx_lclk; // From etx_clocks of etx_clocks.v
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wire tx_lclk90; // From etx_clocks of etx_clocks.v
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// End of automatics
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire tx_access; // From etx_core of etx_core.v
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wire tx_burst; // From etx_core of etx_core.v
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wire tx_io_wait; // From etx_io of etx_io.v
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wire [PW-1:0] tx_packet; // From etx_core of etx_core.v
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wire tx_rd_wait; // From etx_io of etx_io.v
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wire tx_wr_wait; // From etx_io of etx_io.v
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wire txrd_fifo_access; // From etx_fifo of etx_fifo.v
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wire [PW-1:0] txrd_fifo_packet; // From etx_fifo of etx_fifo.v
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wire txrd_fifo_wait; // From etx_core of etx_core.v
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wire txrr_fifo_access; // From etx_fifo of etx_fifo.v
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wire [PW-1:0] txrr_fifo_packet; // From etx_fifo of etx_fifo.v
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wire txrr_fifo_wait; // From etx_core of etx_core.v
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wire txwr_fifo_access; // From etx_fifo of etx_fifo.v
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wire [PW-1:0] txwr_fifo_packet; // From etx_fifo of etx_fifo.v
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wire txwr_fifo_wait; // From etx_core of etx_core.v
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/************************************************************/
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/*Clocks */
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/************************************************************/
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etx_clocks etx_clocks (
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.etx_io_reset (etx_io_reset),
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/*AUTOINST*/
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// Outputs
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_lclk_div4 (tx_lclk_div4),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.etx_reset (etx_reset),
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.chip_resetb (chip_resetb),
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.tx_active (tx_active),
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// Inputs
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.sys_reset (sys_reset),
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.soft_reset (soft_reset),
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.sys_clk (sys_clk));
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/************************************************************/
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/*FIFOs */
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/************************************************************/
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etx_fifo etx_fifo (/*AUTOINST*/
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// Outputs
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.txrd_wait (txrd_wait),
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.txwr_wait (txwr_wait),
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.txrr_wait (txrr_wait),
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.etx_cfg_access (etx_cfg_access),
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.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
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.txrd_fifo_access (txrd_fifo_access),
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.txrd_fifo_packet (txrd_fifo_packet[PW-1:0]),
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.txrr_fifo_access (txrr_fifo_access),
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.txrr_fifo_packet (txrr_fifo_packet[PW-1:0]),
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.txwr_fifo_access (txwr_fifo_access),
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.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
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// Inputs
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.etx_reset (etx_reset),
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.sys_reset (sys_reset),
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.sys_clk (sys_clk),
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.tx_lclk_div4 (tx_lclk_div4),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]),
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.etx_cfg_wait (etx_cfg_wait),
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.txrd_fifo_wait (txrd_fifo_wait),
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.txrr_fifo_wait (txrr_fifo_wait),
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.txwr_fifo_wait (txwr_fifo_wait));
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/***********************************************************/
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/*ELINK CORE LOGIC */
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/***********************************************************/
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/*etx_core AUTO_TEMPLATE ( .tx_access (tx_access),
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.tx_burst (tx_burst),
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.tx_io_wait (tx_io_wait),
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.tx_rd_wait (tx_rd_wait),
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.tx_wr_wait (tx_wr_wait),
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.tx_packet (tx_packet[PW-1:0]),
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.etx_cfg_access (etx_cfg_access),
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.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
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.etx_cfg_wait (etx_cfg_wait),
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.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
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.\(.*\)_access (\1_fifo_access),
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.\(.*\)_wait (\1_fifo_wait),
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);
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*/
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defparam etx_core.ID=ID;
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etx_core etx_core (.clk (tx_lclk_div4),
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.reset (etx_reset),
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/*AUTOINST*/
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// Outputs
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.tx_access (tx_access), // Templated
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.tx_burst (tx_burst), // Templated
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.tx_packet (tx_packet[PW-1:0]), // Templated
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.txrd_wait (txrd_fifo_wait), // Templated
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.txrr_wait (txrr_fifo_wait), // Templated
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.txwr_wait (txwr_fifo_wait), // Templated
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.etx_cfg_access (etx_cfg_access), // Templated
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.etx_cfg_packet (etx_cfg_packet[PW-1:0]), // Templated
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// Inputs
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.tx_io_wait (tx_io_wait), // Templated
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.tx_rd_wait (tx_rd_wait), // Templated
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.tx_wr_wait (tx_wr_wait), // Templated
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.txrd_access (txrd_fifo_access), // Templated
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.txrd_packet (txrd_fifo_packet[PW-1:0]), // Templated
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.txrr_access (txrr_fifo_access), // Templated
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.txrr_packet (txrr_fifo_packet[PW-1:0]), // Templated
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.txwr_access (txwr_fifo_access), // Templated
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.txwr_packet (txwr_fifo_packet[PW-1:0]), // Templated
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.etx_cfg_wait (etx_cfg_wait)); // Templated
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/***********************************************************/
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/*TRANSMIT I/O LOGIC */
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/***********************************************************/
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defparam etx_io.IOSTD_ELINK=IOSTD_ELINK;
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etx_io etx_io (.reset (etx_io_reset),
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/*AUTOINST*/
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// Outputs
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.txo_lclk_p (txo_lclk_p),
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.txo_lclk_n (txo_lclk_n),
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.txo_frame_p (txo_frame_p),
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.tx_io_wait (tx_io_wait),
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.tx_wr_wait (tx_wr_wait),
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.tx_rd_wait (tx_rd_wait),
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// Inputs
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.txi_wr_wait_p (txi_wr_wait_p),
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.txi_wr_wait_n (txi_wr_wait_n),
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.txi_rd_wait_p (txi_rd_wait_p),
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.txi_rd_wait_n (txi_rd_wait_n),
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.tx_packet (tx_packet[PW-1:0]),
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.tx_access (tx_access),
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.tx_burst (tx_burst));
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
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// End:
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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