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aolofsson d2a4d1431b Moving file to elink (makes more sense): 
Each directory should be a self contained "object"
2014-12-14 17:41:07 -05:00
axi/hdl
Merge branch 'elink_redesign' of https://github.com/Parallella/parallella-hw into elink_redesign
2014-11-19 12:29:35 -05:00
common/hdl
Merge branch 'elink_redesign' of https://github.com/Parallella/parallella-hw into elink_redesign
2014-11-19 12:29:35 -05:00
e_mmu
Incremental renaming
2014-12-14 09:14:25 -05:00
e_transmit/hdl
Created a verilog wrapper for the elink transmitter
2014-12-12 20:36:15 -05:00
earb
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
ecfg
Add register definition for ESYSDEBUG...
2014-12-12 12:20:18 -05:00
ecfg_split
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
eclock
Minor fixes for implementation.
2014-11-24 01:57:57 -05:00
edistrib
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
eio_rx
Minor fixes for implementation.
2014-11-24 01:57:57 -05:00
eio_tx
Minor fixes for implementation.
2014-11-24 01:57:57 -05:00
elink
Moving file to elink (makes more sense):
2014-12-14 17:41:07 -05:00
emaxi
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
embox
Adding readback indicator for AXI slave mux
2014-11-06 12:14:49 -05:00
emesh_split
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
emmu
Adding run.sh files for simulation
2014-11-05 20:00:57 -05:00
emon
Adding readback indicator for slave axi mux
2014-11-06 12:15:19 -05:00
eproto_rx
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
eproto_tx
Minor fixes for implementation.
2014-11-24 01:57:57 -05:00
erx/hdl
Adding new verilog modules for receiver and transmitter
2014-12-14 17:18:53 -05:00
esaxi
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
esaxilite/hdl
Adding axi lite interface to be used by various registers
2014-12-14 17:17:04 -05:00
etx/hdl
Adding new verilog modules for receiver and transmitter
2014-12-14 17:18:53 -05:00
gpio/hdl
Reorganizing structure to be IP centric
2014-11-05 14:31:05 -05:00
interfaces
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
memory/hdl
Adding place holders for hard macros
2014-11-06 12:17:56 -05:00
.gitignore
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
Description
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MIT 43 MiB
Languages
Verilog 81.1%
Tcl 10.7%
C 5.6%
Shell 0.8%
Python 0.6%
Other 1.2%