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29 lines
1.3 KiB
Markdown
29 lines
1.3 KiB
Markdown
## Design structure
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elink/ - Top level level AXI elink peripheral
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emaxi/ - AXI master interface
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exaxi/ - AXI slave interface
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exaxilite/ - AXI slave interface for configuration registers
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etx/ - Elink transmit block
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etx_io - Converts packet to high speed serial
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etx_protocol - Creates an elink transaction packet
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etx_arbiter - Selects one of three AXI traffic sources (rd, wr, rr)
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s_rq_fifo - Read request fifo for slave AXI interface
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s_wr_fifo - Write request fifo for slave AXI interface
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m_rr_fifo - Read response fifo for master AXI interface
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erx/ - Elink receiver block
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etx_io - Converts serial packet received to parallel
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etx_protocol - Converts the elink packet to 104 bit emesh transaction
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etx_disty - Decodes emesh transaction and sends to AXI interface
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emmu - Translates the dstaddr of incoming transaction
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m_rq_fifo - Read request fifo for master AXI interface
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m_wr_fifo - Write request fifo for master AXI interface
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s_rr_fifo - Read response fifo for slave AXI interface
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ecfg/ - Configurationr register file for elink
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embox/ - Mail box (with interrupt output)
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eclock/ - Clock generator
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