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b0b9315bf1
-this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created)
88 lines
2.7 KiB
Verilog
88 lines
2.7 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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module esaxilite (/*AUTOARG*/
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// Outputs
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s_axi_arready, s_axi_awready, s_axi_bresp, s_axi_bvalid,
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s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_wready, mi_clk,
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mi_en, mi_we, mi_addr, mi_din,
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// Inputs
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s_axi_aclk, s_axi_aresetn, s_axi_araddr, s_axi_arprot,
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s_axi_arvalid, s_axi_awaddr, s_axi_awprot, s_axi_awvalid,
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s_axi_bready, s_axi_rready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
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mi_rd_data
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);
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parameter RFAW = 13;
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/*****************************/
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/*AXI 32 bit lite interface */
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/*****************************/
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input s_axi_aclk;
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input s_axi_aresetn;
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//read address channel
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input [RFAW-1:0] s_axi_araddr;
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input [2:0] s_axi_arprot;
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output s_axi_arready;
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input s_axi_arvalid;
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//write address channel
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input [RFAW-1:0] s_axi_awaddr;
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input [2:0] s_axi_awprot;
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output s_axi_awready;
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input s_axi_awvalid;
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//buffered read response channel
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input s_axi_bready;
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output [1:0] s_axi_bresp;
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output s_axi_bvalid;
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//read channel
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output [31:0] s_axi_rdata;
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input s_axi_rready;
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output [1:0] s_axi_rresp;
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output s_axi_rvalid;
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//write channel
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input [31:0] s_axi_wdata;
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output s_axi_wready;
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input [3:0] s_axi_wstrb;
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input s_axi_wvalid;
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/*****************************/
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/*Simple memory interface */
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/*****************************/
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output mi_clk;
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output mi_en;
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output mi_we;
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output [RFAW-1:0] mi_addr;
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output [31:0] mi_din;
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input [31:0] mi_rd_data;
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//PUT BRAM CONTROLLER HERE
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assign mi_clk = s_axi_aclk;
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assign mi_en = 1'b0;
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assign mi_we = 1'b0;
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assign mi_addr[RFAW-1:0] = {(RFAW){1'b0}};
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assign mi_din[31:0] = 32'b0;
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//TODO: Insert BRAM controller or similar interface here
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endmodule // esaxilite
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