mirror of
https://github.com/aolofsson/oh.git
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111 lines
3.4 KiB
Verilog
111 lines
3.4 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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/*
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########################################################################
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Generic small FIFO using distributed memory
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Caution: There is no protection against overflow or underflow,
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driving logic should avoid wen on full or ren on empty.
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########################################################################
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*/
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module fifo_sync
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#(
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// Address width (must be 5 => 32-deep FIFO)
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parameter AW = 5,
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// Data width
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parameter DW = 16
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)
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(
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input clk,
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input reset,
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input [DW-1:0] wr_data,
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input wr_en,
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input rd_en,
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output wire [DW-1:0] rd_data,
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output reg rd_empty,
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output reg wr_full
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);
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reg [AW-1:0] waddr;
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reg [AW-1:0] raddr;
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reg [AW-1:0] count;
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always @ ( posedge clk ) begin
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if( reset )
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begin
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waddr <= 1'b0;
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raddr <= 1'b0;
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count <= 1'b0;
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rd_empty <= 1'b1;
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wr_full <= 1'b0;
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end else
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begin
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if( wr_en & rd_en )
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begin
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waddr <= waddr + 'd1;
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raddr <= raddr + 'd1;
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end
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else if( wr_en )
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begin
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waddr <= waddr + 'd1;
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count <= count + 'd1;
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rd_empty <= 1'b0;
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if( & count )
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wr_full <= 1'b1;
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end
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else if( rd_en )
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begin
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raddr <= raddr + 'd1;
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count <= count - 'd1;
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wr_full <= 1'b0;
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if( count == 'd1 )
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rd_empty <= 1'b1;
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end
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end // else: !if( reset )
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end // always @ ( posedge clk )
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`ifdef TARGET_XILINX
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genvar dn;
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generate for(dn=0; dn<DW; dn=dn+1)
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begin : genbits
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RAM32X1D RAM32X1D_inst
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(
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.DPO(rd_data[dn] ), // Read-only 1-bit data output
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.SPO(), // Rw/ 1-bit data output
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.A0(waddr[0]), // Rw/ address[0] input bit
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.A1(waddr[1]), // Rw/ address[1] input bit
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.A2(waddr[2]), // Rw/ address[2] input bit
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.A3(waddr[3]), // Rw/ address[3] input bit
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.A4(waddr[4]), // Rw/ address[4] input bit
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.D(wr_data[dn]), // Write 1-bit data input
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.DPRA0(raddr[0]), // Read-only address[0] input bit
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.DPRA1(raddr[1]), // Read-only address[1] input bit
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.DPRA2(raddr[2]), // Read-only address[2] input bit
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.DPRA3(raddr[3]), // Read-only address[3] input bit
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.DPRA4(raddr[4]), // Read-only address[4] input bit
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.WCLK(clk), // Write clock input
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.WE(wr_en) // Write enable input
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);
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end
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endgenerate
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`endif
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endmodule // syncfifo
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