Andreas Olofsson fd7aff5dd8 Fixing warning messages in chip synthesis tool ...

- Don't fight the tools
- No way to remove these warnings and I don't want to have to tell everyone to include maging "don't output this kind of warning flags" that are global to a project...that's just bad practice.
- Didn't take many minutes to remove these warnings and now synthesis runs through with 0 warnings ... much cleaner.. inspires more confidence

2016-02-12 11:04:52 -05:00

..

docs

Adding emesh timing diagram

2016-02-04 20:45:31 -05:00

dv

Cleaning up register interface

2016-01-11 17:35:53 -05:00

hdl

Fixing warning messages in chip synthesis tool

2016-02-12 11:04:52 -05:00