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fd7aff5dd8
- Don't fight the tools - No way to remove these warnings and I don't want to have to tell everyone to include maging "don't output this kind of warning flags" that are global to a project...that's just bad practice. - Didn't take many minutes to remove these warnings and now synthesis runs through with 0 warnings ... much cleaner.. inspires more confidence
82 lines
2.1 KiB
Verilog
82 lines
2.1 KiB
Verilog
module emesh_mux (/*AUTOARG*/
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// Outputs
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wait_out, access_out, packet_out,
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// Inputs
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access_in, packet_in, wait_in
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);
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//#####################################################################
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//# PARAMETERS
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//#####################################################################
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parameter AW = 32;
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parameter PW = 2 * AW + 40;
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parameter N = 99;
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parameter CFG = "STATIC"; //Arbitration configuration
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//"STATIC" fixed priority
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//"DYNAMIC" round robin priority
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//Incoming transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//Outgoing transaction
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output access_out;
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output [PW-1:0] packet_out;
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input wait_in;
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//#####################################################################
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//# BODY
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//#####################################################################
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//local variables
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wire [N-1:0] grants;
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reg [PW-1:0] packet_out;
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integer i;
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//arbiter
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generate
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if(CFG=="STATIC")
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begin : arbiter_static
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oh_arbiter #(.N(N))
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arbiter(// Outputs
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.grants (grants[N-1:0]),
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// Inputs
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.requests (access_in[N-1:0])
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);
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end
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else if (CFG=="DYNAMIC")
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begin : arbiter_dynamic
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`ifdef TARGET_SIM
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initial
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$display("ROUND ROBIN ARBITER NOT IMPLEMENTED\n");
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`endif
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end
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endgenerate
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//access signal
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assign access_out = |(access_in[N-1:0]);
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//raise wait signals
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assign wait_out[N-1:0] = access_in[N-1:0] & (~grants[N-1:0] | {(N){wait_in}});
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//parametrized mux
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always @*
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begin
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packet_out[PW-1:0] = 'b0;
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for(i=0;i<N;i=i+1)
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packet_out[PW-1:0] = packet_out[PW-1:0] | {(PW){grants[i]}} & packet_in[((i+1)*PW-1)-:PW];
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end
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endmodule // mesh_mux
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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