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213 lines
6.3 KiB
Verilog
213 lines
6.3 KiB
Verilog
`include "elink_regmap.v"
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/*
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*
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* This module converts the packet interface to a 64bit wide format
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* suitable for sending out to a parallel to serial shift register.
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* The frame signal is sent along together with the data making.
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* The goal is to minimize the amount of logic done on the high speed
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* domain.
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*
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*
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*/
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module etx_protocol (/*AUTOARG*/
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// Outputs
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etx_rd_wait, etx_wr_wait, tx_burst, tx_access, tx_data_slow,
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tx_frame_slow,
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// Inputs
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nreset, clk, etx_access, etx_packet, tx_enable, burst_enable,
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gpio_data, gpio_enable, tx_rd_wait, tx_wr_wait
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);
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parameter PW = 104;
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parameter AW = 32;
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parameter DW = 32;
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parameter ID = 12'h000;
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//Clock/reset
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input nreset;
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input clk;
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//System side
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input etx_access;
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input [PW-1:0] etx_packet;
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//Pushback signals
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output etx_rd_wait;
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output etx_wr_wait;
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//Config interface
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input tx_enable; //transmit enable
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input burst_enable; //Enables bursting
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input [8:0] gpio_data; //TODO
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input gpio_enable; //TODO
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output tx_burst; //for TXSTATUS
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output tx_access; //for TXMON
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//Interface to IO
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output [63:0] tx_data_slow;
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output [3:0] tx_frame_slow;
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input tx_rd_wait;
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input tx_wr_wait;
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//################################################################
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//# Local regs & wires
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//################################################################
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reg [2:0] tx_state;
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reg [PW-1:0] tx_packet;
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wire etx_write;
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wire [1:0] etx_datamode;
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wire [4:0] etx_ctrlmode;
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wire [AW-1:0] etx_dstaddr;
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wire [DW-1:0] etx_data;
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wire tx_write;
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wire [1:0] tx_datamode;
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wire [4:0] tx_ctrlmode;
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wire [AW-1:0] tx_dstaddr;
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wire [DW-1:0] tx_data;
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wire [AW-1:0] tx_srcaddr;
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wire burst_match;
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wire burst_type_match;
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wire [31:0] burst_addr;
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wire burst_addr_match;
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wire burst_in;
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wire adjust;
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wire current_match;
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wire next_match;
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wire tx_burst_in;
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//##############################################################
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//# Packet Pipeline
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//##############################################################
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packet2emesh #(.AW(AW))
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p2m0 (
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.write_in (etx_write),
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.datamode_in (etx_datamode[1:0]),
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.ctrlmode_in (etx_ctrlmode[4:0]),
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.dstaddr_in (etx_dstaddr[31:0]),
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.data_in (),
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.srcaddr_in (),
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.packet_in (etx_packet[PW-1:0]));//input
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//Hold transaction while waiting
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always @ (posedge clk)
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if(~etx_wait)
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tx_packet[PW-1:0] <= etx_packet[PW-1:0];
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//the IO pipeline flushes out
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packet2emesh #(.AW(AW))
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p2m1 (
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.write_in (tx_write),
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.datamode_in (tx_datamode[1:0]),
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.ctrlmode_in (tx_ctrlmode[4:0]),
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.dstaddr_in (tx_dstaddr[31:0]),
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.data_in (tx_data[31:0]),
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.srcaddr_in (tx_srcaddr[31:0]),
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.packet_in (tx_packet[PW-1:0]));//input
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//#############################
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//# Burst Detection
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//#############################
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assign burst_addr_match = ((tx_dstaddr[31:0]+32'h8) == etx_dstaddr[31:0]);
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assign current_match = tx_access &
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tx_write &
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(tx_datamode[1:0]==2'b11) &
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(tx_ctrlmode[3:0]==4'b0000);
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assign next_match = etx_access & //BUG: should be valid?
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etx_write &
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(etx_datamode[1:0]==2'b11) &
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(etx_ctrlmode[3:0]==4'b0000);
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assign tx_burst = burst_enable &
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~tx_wait &
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current_match &
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next_match &
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burst_addr_match;
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reg tx_burst_reg;
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always @ (posedge clk)
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tx_burst_reg <=tx_burst;
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//############################################################
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//# TRANSMIT STATE MACHINE
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//#############################################################
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assign etx_valid = tx_enable &
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etx_access &
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~(etx_dstaddr[31:20]==ID) &
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~tx_wait;
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`define TX_IDLE 3'b000
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`define TX_START 3'b001
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`define TX_ACK 3'b010
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`define TX_BURST 3'b011
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`define TX_WAIT 3'b100
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always @ (posedge clk)
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if(!nreset)
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tx_state[2:0] <= `TX_IDLE;
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else
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case (tx_state[2:0])
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`TX_IDLE: tx_state[2:0] <= etx_valid ? `TX_START : `TX_IDLE;
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`TX_START: tx_state[2:0] <= `TX_ACK;
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`TX_ACK: tx_state[2:0] <= tx_burst ? `TX_BURST :
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etx_valid ? `TX_START :
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`TX_IDLE;
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`TX_BURST: tx_state[2:0] <= tx_burst ? `TX_BURST : `TX_IDLE;
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endcase // case (tx_state[2:0])
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assign tx_ack_wait = (tx_state[1:0]==`TX_START);
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assign tx_access = (tx_state[1:0]==`TX_START) |
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(tx_state[1:0]==`TX_BURST);
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//#######################################
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//# Wait propagation circuit backwards
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//########################################
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wire [63:0] tx_cycle1;
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wire [63:0] tx_cycle2;
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assign tx_frame_slow[3:0] = (tx_state[1:0]==`TX_START) ? 4'b0111 :
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(tx_state[1:0]!=`TX_IDLE) ? 4'b1111 :
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4'b0000;
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assign tx_cycle1[63:0] = {tx_dstaddr[11:0],tx_datamode[1:0],tx_write,tx_access, //47:32
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tx_dstaddr[27:12], //31:16
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~tx_write,5'b0,tx_burst_reg,1'b0, //8-15
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tx_ctrlmode[3:0],tx_dstaddr[31:28], //0-7
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16'b0 //garbage
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};
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assign tx_cycle2[63:0] = {tx_srcaddr[15:0], //48-63
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tx_srcaddr[31:16], //32-47
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tx_data[15:0], //16-31
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tx_data[31:16] //0-15
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};
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assign tx_data_slow[63:0] = (tx_state[2:0]==`TX_START) ? tx_cycle1[63:0] :
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tx_cycle2[63:0];
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//#######################################
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//# Wait propagation circuit backwards
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//########################################
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//immediate wait for state machine
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assign tx_wait = tx_wr_wait | tx_rd_wait;
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//wait for data
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assign etx_wr_wait = (tx_wr_wait | tx_ack_wait );
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assign etx_rd_wait = (tx_rd_wait | tx_ack_wait );
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assign etx_wait = etx_wr_wait | etx_rd_wait;
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endmodule // etx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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