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67 lines
1.4 KiB
Verilog
67 lines
1.4 KiB
Verilog
module oh_counter (/*AUTOARG*/
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// Outputs
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count, zero,
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// Inputs
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clk, nreset, en, load, wdata
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);
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//###############################################################
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//# Interface
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//###############################################################
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parameter DW = 64;
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parameter TYPE = "BINARY"; //BINARY, GRAY, LFSR
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//clock interface
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input clk;
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input nreset;
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//counter control
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input en; //counter enabled
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input load; //loads new start value
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input [DW-1:0] wdata; //write data
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//outputs
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output [DW-1:0] count; //current count value
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output zero; //counter is zero
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//###############################################################
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//# Interface
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//###############################################################
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reg [DW-1:0] count;
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always @(posedge clk or negedge)
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if(nreset)
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count[DW-1:0] = 'b0;
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else if(load)
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count[DW-1:0] = wdata[DW-1:0];
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else if (en)
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count[DW-1:0] = count_in[DW-1:0];
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generate
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if(TYPE=="BINARY")
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begin
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assign count_in[DW-1:0] = count[DW-1:0] + 1'b1;
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end
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else if (TYPE=="GRAY")
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begin
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initial
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$display ("NOT IMPLEMENTED");
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end
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else if (TYPE=="LFSR")
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begin
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initial
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$display ("NOT IMPLEMENTED");
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end
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endgenerate
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endmodule // oh_counter
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