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97 lines
2.4 KiB
Verilog
97 lines
2.4 KiB
Verilog
module oh_fifo_sync (/*AUTOARG*/
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// Outputs
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dout, empty, full, almost_full, count,
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// Inputs
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clk, nreset, din, wr_en, rd_en
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);
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//#####################################################################
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//# PARAMETERS
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//#####################################################################
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parameter DEPTH = 4;
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parameter DW = 104;
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parameter ALMOST_FULL = DEPTH-1;
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localparam AW = $clog2(DEPTH);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//clk/reset
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input clk;
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input nreset;
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//write port
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input [DW-1:0] din;
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input wr_en;
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//Read port
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input rd_en;
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output [DW-1:0] dout;
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//Status
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output empty;
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output full;
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output almost_full;
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output [AW:0] count;
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//#####################################################################
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//# BODY
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//#####################################################################
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reg [AW-1:0] wr_addr;
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reg [AW-1:0] rd_addr;
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reg [AW:0] count;
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assign empty = (count[AW:0]==0);
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assign almost_full = (count[AW:0] >=ALMOST_FULL);
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assign full = (count==DEPTH);
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always @ ( posedge clk or negedge nreset)
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if(!nreset)
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begin
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wr_addr[AW-1:0] <= 'd0;
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rd_addr[AW-1:0] <= 'b0;
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count[AW:0] <= 'b0;
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end
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else if(wr_en & rd_en)
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begin
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wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
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rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
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end
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else if(wr_en)
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begin
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wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
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count[AW:0] <= count[AW:0] + 'd1;
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end
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else if(rd_en)
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begin
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rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
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count[AW:0] <= count[AW:0] - 'd1;
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end
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// GENERIC DUAL PORTED MEMORY
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defparam mem.DW=DW;
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defparam mem.AW=AW;
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oh_memory_dp
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#(.DW(DW),
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.AW(AW))
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mem (
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// Outputs
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.rd_data (dout[DW-1:0]),
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// Inputs
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.wr_clk (clk),
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.wr_en ({(DW/8){wr_en}}),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_data (din[DW-1:0]),
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.rd_clk (clk),
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.rd_en (rd_en),
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.rd_addr (rd_addr[AW-1:0]));
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endmodule // fifo_sync
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// Local Variables:
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// verilog-library-directories:(".")
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// End:
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