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oh/accelerator/fpga/ip_params.tcl
2016-01-20 18:45:20 -05:00

23 lines
411 B
Tcl

# NOTE: See UG1118 for more information
set design axi_accelerator
set projdir ./
set root "../.."
set partname "xc7z020clg400-1"
set hdl_files [list \
$root/accelerator/hdl \
$root/common/hdl/ \
$root/emesh/hdl \
$root/emmu/hdl \
$root/axi/hdl \
$root/emailbox/hdl \
$root/edma/hdl \
$root/elink/hdl \
]
set ip_files []
set constraints_files []