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67 lines
2.2 KiB
Verilog
67 lines
2.2 KiB
Verilog
//#############################################################################
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//# Function: Clock domain crossing FIFO #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_fifo_cdc # (parameter DW = 104, //FIFO width
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parameter DEPTH = 32, //FIFO depth (entries)
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parameter TARGET = "GENERIC" //XILINX,ALTERA,GENERIC
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)
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(
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input nreset, // shared domain async active low reset
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input clk_in, // write clock
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input access_in, // write access
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input [DW-1:0] packet_in, // write packet
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output wait_out, // write pushback
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input clk_out, //read clock
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output reg access_out, //read access
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output [DW-1:0] packet_out, //read packet
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input wait_in, // read pushback
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output prog_full, // fifo is half full
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output full, // fifo is full
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output empty // fifo is empty
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);
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// local wires
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wire wr_en;
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wire rd_en;
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wire io_nreset;
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// parametric async fifo
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oh_fifo_async #(.TARGET(TARGET),
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.DW(DW),
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.DEPTH(DEPTH))
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fifo (.prog_full (prog_full),
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.full (full),
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.rd_count (),
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.nreset (nreset),
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.dout (packet_out[DW-1:0]),
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.empty (empty),
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.wr_clk (clk_in),
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.rd_clk (clk_out),
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.wr_en (wr_en),
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.din (packet_in[DW-1:0]),
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.rd_en (rd_en));
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// FIFO control logic
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assign wr_en = access_in;
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assign rd_en = ~empty & ~wait_in;
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assign wait_out = prog_full; //wait_out should stall access_in signal
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// pipeline access_out signal
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always @ (posedge clk_out or negedge io_nreset)
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if(!io_nreset)
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access_out <= 1'b0;
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else if(~wait_in)
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access_out <= rd_en;
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// be safe, synchronize reset with clk_out
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oh_rsync sync_reset(.nrst_out (io_nreset),
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.clk (clk_out),
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.nrst_in (nreset));
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endmodule // oh_fifo_cdc
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