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44 lines
1.2 KiB
Verilog
44 lines
1.2 KiB
Verilog
//#############################################################################
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//# Function: Rising Edge Sampled Register #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_reg1 #(parameter DW = 1 // data width
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)
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( input nreset, //async active low reset
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input clk, // clk, latch when clk=0
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input [DW-1:0] in, // input data
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output [DW-1:0] out // output data (stable/latched when clk=1)
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);
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localparam ASIC = `CFG_ASIC;
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generate
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if(ASIC)
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begin : g0
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asic_reg1 ireg [DW-1:0] (.nreset(nreset),
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.clk(clk),
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.in(in[DW-1:0]),
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.out(out[DW-1:0]));
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end
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else
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begin
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reg [DW-1:0] out_reg;
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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out_reg[DW-1:0] <= 'b0;
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else
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out_reg[DW-1:0] <= in[DW-1:0];
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assign out[DW-1:0] = out_reg[DW-1:0];
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end // else: !if(ASIC)
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endgenerate
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endmodule // ohr_reg1
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