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136 lines
3.8 KiB
Verilog
136 lines
3.8 KiB
Verilog
`include "elink_regmap.vh"
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module elink_cfg (/*AUTOARG*/
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// Outputs
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txwr_gated_access, etx_soft_reset, erx_soft_reset, clk_config,
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chipid,
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// Inputs
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clk, nreset, txwr_access, txwr_packet
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);
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parameter RFAW = 6; // 32 registers for now
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parameter PW = 104; // 32 registers for now
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parameter ID = 12'h000;
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parameter DEFAULT_CHIPID = 12'h808;
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/******************************/
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/*Clock/reset */
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/******************************/
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input clk;
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input nreset; // POR "hard reset"
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/******************************/
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/*REGISTER ACCESS */
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/******************************/
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input txwr_access;
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input [PW-1:0] txwr_packet;
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/******************************/
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/*FILTERED WRITE FOR TX FIFO */
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/******************************/
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output txwr_gated_access;
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/******************************/
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/*Outputs */
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/******************************/
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output etx_soft_reset; // tx soft reset (level)
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output erx_soft_reset; // rx soft reset (level)
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output [15:0] clk_config; // clock settings (for pll)
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output [11:0] chipid; // chip-id for Epiphany
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/*------------------------CODE BODY---------------------------------------*/
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//registers
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reg [1:0] ecfg_reset_reg;
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reg [15:0] ecfg_clk_reg;
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reg [11:0] ecfg_chipid;
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reg [31:0] mi_dout;
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//wires
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wire ecfg_read;
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wire ecfg_write;
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wire ecfg_clk_write;
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wire ecfg_chipid_write;
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wire ecfg_reset_write;
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wire mi_en;
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wire [31:0] mi_addr;
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wire [31:0] mi_din;
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wire mi_we;
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packet2emesh #(.AW(32))
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pe2 (
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// Outputs
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.write_in (mi_we),
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.datamode_in (),
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.ctrlmode_in (),
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.dstaddr_in (mi_addr[31:0]),
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.data_in (mi_din[31:0]),
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.srcaddr_in (),
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// Inputs
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.packet_in (txwr_packet[PW-1:0])
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);
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/*****************************/
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/*ADDRESS DECODE LOGIC */
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/*****************************/
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assign mi_en = txwr_access &
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(mi_addr[31:20]==ID) &
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(mi_addr[10:8]==3'h2);
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//read/write decode
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assign ecfg_write = mi_en & mi_we;
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assign ecfg_read = mi_en & ~mi_we;
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//Config write enables
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assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_RESET);
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assign ecfg_clk_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CLK);
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assign ecfg_chipid_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CHIPID);
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/*****************************/
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/*FILTER ACCESS */
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/*****************************/
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assign txwr_gated_access = txwr_access & ~(ecfg_reset_write |
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ecfg_clk_write |
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ecfg_chipid_write);
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//###########################
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//# RESET REG (ASYNC)
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//###########################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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ecfg_reset_reg[1:0] <= 'b0;
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else if (ecfg_reset_write)
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ecfg_reset_reg[1:0] <= mi_din[1:0];
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assign etx_soft_reset = ecfg_reset_reg[0];
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assign erx_soft_reset = ecfg_reset_reg[1];
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//###########################
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//# CCLK/LCLK (PLL)
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//###########################
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//TODO: implement!
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed
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else if (ecfg_clk_write)
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ecfg_clk_reg[15:0] <= mi_din[15:0];
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assign clk_config[15:0] = ecfg_clk_reg[15:0];
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//###########################
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//# CHIPID
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//###########################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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ecfg_chipid[11:0] <= DEFAULT_CHIPID;
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else if (ecfg_chipid_write)
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ecfg_chipid[11:0] <= mi_din[11:0];
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assign chipid[11:0]=ecfg_chipid[11:0];
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endmodule // ecfg_elink
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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