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d7508f9938
-Set VCO_MULT to 1 for PLL. Dirty hack to allow the RX clk to phase align with the input. Otherwise, if you multiply the VCO clock and then divide, you get a random phase alignment the way the current clock divider is written. -Changed the fifo_cdc to 32 entries. Forgot that I had changed the fifo_cdc to hard coded per number of entries. Really need to have a parametrixed model that works!!
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OH!
Open Hardware (Pure and Simple)
(work in progress...)
Building
git clone https://github.com/parallella/oh.git
cd oh
mkdir build
cd build
../configure
make elink