Andreas Olofsson d7508f9938 DV cleanup ...

-Set VCO_MULT to 1 for PLL. Dirty hack to allow the RX clk to phase align with the input. Otherwise, if you multiply the VCO clock and then divide, you get a random phase alignment the way the current clock divider is written.
-Changed the fifo_cdc to 32 entries. Forgot that I had changed the fifo_cdc to hard coded per number of entries. Really need to have a parametrixed model that works!!

2015-09-14 21:58:52 -04:00

..

dv_ecfg.v

Cleanup

2015-04-11 00:12:57 -04:00

dv_elink_system.v

File cleanup

2015-04-23 18:10:07 -04:00

dv_elink_tb.v

Adding bursting to test bench

2015-05-18 15:37:46 -04:00

dv_elink.v

DV cleanup

2015-09-14 21:58:52 -04:00

elink_e16_model.v

E16 model cleanup

2015-05-02 21:28:09 -04:00

elink.cmd

Update dv paths

2015-07-02 16:48:14 -04:00

emesh_monitor.v

Packet interface changes

2015-04-23 18:09:16 -04:00

run.sh

Adding sim parameter

2015-09-11 18:25:08 -04:00

signals.gtkw

Milestone: WRITE AND READ FROM HOST WORKS!

2015-04-21 17:16:20 -04:00

test.memh

DV cleanup

2015-09-14 21:58:52 -04:00