mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-17 20:02:53 +08:00
983c4db449
- Using new packet interface - Adding active signal, indicating that link is ready. This way you don't need to guess when the link is ready (no magic constants) - Removed register on por reset input to get rid of x on startup.
419 lines
12 KiB
Verilog
419 lines
12 KiB
Verilog
/*###########################################################################
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# Function: Clock and reset generator
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#
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# tx_lclk_div4 - Parallel data clock (125Mhz)
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#
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# tx_lclk - DDR data clock (500MHz)
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#
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# tx_lclk90 - DDR "Clock" for IO (500MHz)
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#
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# rx_lclk - High speed RX clock for IO (300MHz phase shifted)
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#
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# rx_lclk_div4 - Low speed RX clock for logic (75MHz)
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############################################################################
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*/
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`include "elink_constants.v"
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module eclocks (/*AUTOARG*/
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// Outputs
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tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk, rx_lclk_div4, e_cclk_p,
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e_cclk_n, elink_reset, e_resetb,
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// Inputs
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reset, elink_en, sys_clk, rx_clkin
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);
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//TODO: change to parameter
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`ifdef TARGET_SIMPLE
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parameter RCW = 4; // reset counter width
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`else
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parameter RCW = 8; // reset counter width
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`endif
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//Frequency Settings (Mhz)
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parameter FREQ_SYSCLK = 100;
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parameter FREQ_RXCLK = 300;
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parameter FREQ_TXCLK = 300;
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parameter FREQ_IDELAY = 200;
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parameter FREQ_CCLK = 600;
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parameter TXCLK_PHASE = 90; //txclk phase shift
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parameter RXCLK_PHASE = 0; //270; //-90 deg rxclk phase shift
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//VCO multiplers
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parameter MMCM_VCO_MULT = 12; //TX + CCLK
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parameter PLL_VCO_MULT = 4; //RX
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//Input clock, reset, config interface
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input reset; // async input reset
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input elink_en; // elink enable (from pin or register)
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//Main input clocks
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input sys_clk; // always on input clk cclk/TX MMCM
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input rx_clkin; // input clk for RX only PLL
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//TX Clocks
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output tx_lclk; // tx clock for DDR IO
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output tx_lclk90; // tx output clock shifted by 90 degrees
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output tx_lclk_div4; // tx slow clock for logic
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//RX Clocks
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output rx_lclk; // rx high speed clock for DDR IO
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output rx_lclk_div4; // rx slow clock for logic
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//Epiphany "free running" clock
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output e_cclk_p, e_cclk_n;
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//Reset
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output elink_reset; // reset for elink logic & IO
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output e_resetb; // reset fpr Epiphany chip
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//Don't touch these! (derived parameters)
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localparam real SYSCLK_PERIOD = 1000.000000/FREQ_SYSCLK;
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localparam real RXCLK_PERIOD = 1000.000000/FREQ_RXCLK;
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localparam integer TXCLK_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_TXCLK;
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localparam integer CCLK_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_CCLK;
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localparam integer IREF_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_IDELAY;
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localparam integer RXCLK_DIVIDE = PLL_VCO_MULT;
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//############
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//# WIRES
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//############
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//CCLK
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wire cclk_reset;
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wire cclk_i;
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wire cclk_bufio;
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wire cclk_oddr;
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//Idelay controller
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wire idelay_reset;
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wire idelay_ready; //ignore this?
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wire idelay_ref_clk_i;
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wire idelay_ref_clk;
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//RX
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wire rx_lclk_i;
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wire rx_lclk_div4_i;
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//TX
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wire tx_lclk_i;
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wire tx_lclk90_i;
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wire tx_lckl_div4_i;
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//MMCM & PLL
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wire cclk_fb_in;
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wire cclk_fb_out;
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wire lclk_fb_i;
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wire pll_reset;
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wire cclk_locked;
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wire lclk_fb_in;
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wire lclk_fb_out;
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reg cclk_locked_reg;
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reg cclk_locked_sync;
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reg rx_locked_reg;
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reg rx_locked_sync;
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wire lclk_locked;
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//###########################
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// RESET STATE MACHINE
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//###########################
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reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
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reg heartbeat;
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wire reset_in;
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reg reset_sync;
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reg [2:0] reset_state;
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//wrap around counter that generates a 1 cycle heartbeat
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//free running counter...
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always @ (posedge sys_clk)
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begin
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reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
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heartbeat <= ~(|reset_counter[RCW-1:0]);
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end
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//two clock synchronizer
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always @ (posedge sys_clk)
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begin
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//TODO: Does rx_lclk always run when cclk does? Restb ?
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rx_locked_reg <= lclk_locked;
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rx_locked_sync <= rx_locked_reg;
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cclk_locked_reg <= cclk_locked; // & clk_locked
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cclk_locked_sync <= cclk_locked_reg;
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end
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`define RESET_ALL 3'b000
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`define START_CCLK 3'b001
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`define STOP_CCLK 3'b010
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`define START_EPIPHANY 3'b011
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`define HOLD_IT 3'b100
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`define TX_ACTIVE 3'b101
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`define ACTIVE 3'b110
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//Reset sequence state machine
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always @ (posedge sys_clk or posedge reset)
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if(reset)
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reset_state[2:0] <= `RESET_ALL;
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else if(heartbeat)
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case(reset_state[2:0])
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`RESET_ALL :
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reset_state[2:0] <= `START_CCLK;
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`START_CCLK :
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if(cclk_locked_sync)
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reset_state[2:0] <= `STOP_CCLK;
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`STOP_CCLK :
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reset_state[2:0] <= `START_EPIPHANY;
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`START_EPIPHANY :
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reset_state[2:0] <= `HOLD_IT;
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`HOLD_IT :
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if(cclk_locked_sync)
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reset_state[2:0] <= `TX_ACTIVE;
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`TX_ACTIVE :
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reset_state[2:0] <= `ACTIVE;
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`ACTIVE:
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if(~elink_en)
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reset_state[2:0] <= `RESET_ALL; //stay there until nex reset
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endcase // case (reset_state[2:0])
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//reset PLL during 'reset' and during quiet time around reset edge
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//TODO: this is a bug if the RX gets a clock that is not a turnaround from TX
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assign pll_reset = (reset_state[2:0] != `ACTIVE);
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assign idelay_reset = (reset_state[2:0]==`RESET_ALL) |
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(reset_state[2:0]==`START_CCLK) |
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reset;
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assign cclk_reset = (reset_state[2:0]==`RESET_ALL) |
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(reset_state[2:0]==`STOP_CCLK) |
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(reset_state[2:0]==`START_EPIPHANY) |
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reset
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;
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assign e_resetb = (reset_state[2:0]==`START_EPIPHANY) |
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(reset_state[2:0]==`HOLD_IT) |
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(reset_state[2:0]==`ACTIVE) |
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(reset_state[2:0]==`TX_ACTIVE)
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;
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assign elink_reset = reset |
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~((reset_state[2:0] == `TX_ACTIVE) |
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(reset_state[2:0] == `ACTIVE));
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`ifdef TARGET_XILINX
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//###########################
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// MMCM FOR TXCLK + CCLK
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//###########################
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MMCME2_ADV
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#(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT_F(MMCM_VCO_MULT),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(SYSCLK_PERIOD),
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.CLKOUT0_DIVIDE_F(CCLK_DIVIDE), //cclk_c
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.CLKOUT1_DIVIDE(TXCLK_DIVIDE), //tx_lclk
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.CLKOUT2_DIVIDE(TXCLK_DIVIDE), //tx_lclk90
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.CLKOUT3_DIVIDE(TXCLK_DIVIDE*4), //tx_lclk_div4
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.CLKOUT4_DIVIDE(IREF_DIVIDE), //idelay_refclk
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.CLKOUT5_DIVIDE(128), //
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.CLKOUT6_DIVIDE(128), //
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(TXCLK_PHASE),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.CLKOUT6_PHASE(0.0),
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.DIVCLK_DIVIDE(1.0),
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.REF_JITTER1(0.01),
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.STARTUP_WAIT("FALSE")
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) mmcm_cclk
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(
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.CLKOUT0(cclk_i),
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.CLKOUT0B(),
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.CLKOUT1(tx_lclk_i),
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.CLKOUT1B(),
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.CLKOUT2(tx_lclk90_i),
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.CLKOUT2B(),
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.CLKOUT3(tx_lclk_div4_i),
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.CLKOUT3B(),
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.CLKOUT4(idelay_ref_clk_i),
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.CLKOUT5(),
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.CLKOUT6(),
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.PWRDWN(1'b0),
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.RST(cclk_reset), //reset
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.CLKFBIN(cclk_fb_in),
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.CLKFBOUT(cclk_fb_out), //feedback clock
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.CLKIN1(sys_clk), //input clock
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(7'b0),
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.DCLK(1'b0),
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.DEN(1'b0),
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.DI(16'b0),
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.DWE(1'b0),
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.DRDY(),
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.DO(),
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.LOCKED(cclk_locked), //locked indicator
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.PSCLK(1'b0),
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.PSEN(1'b0),
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.PSDONE(),
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.PSINCDEC(1'b0),
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.CLKFBSTOPPED(),
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.CLKINSTOPPED()
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);
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//Idelay ref clock buffer
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BUFG idelay_ref_bufg_i(.I(idelay_ref_clk_i), .O(idelay_ref_clk));
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//Feedback buffer
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BUFG cclk_fb_bufg_i(.I(cclk_fb_out), .O(cclk_fb_in));
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//Tx clock buffers
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BUFG tx_lclk_bufg_i (.I(tx_lclk_i), .O(tx_lclk));
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BUFG tx_lclk_div4_bufg_i (.I(tx_lclk_div4_i), .O(tx_lclk_div4));
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BUFG tx_lclk90_bufg_i (.I(tx_lclk90_i), .O(tx_lclk90));
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//###########################
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// PLL RX
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//###########################
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PLLE2_ADV
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#(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT(PLL_VCO_MULT),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(RXCLK_PERIOD),
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.CLKOUT0_DIVIDE(128),
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.CLKOUT1_DIVIDE(128),
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.CLKOUT2_DIVIDE(128),
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.CLKOUT3_DIVIDE(128),
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.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
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.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(RXCLK_PHASE),
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.CLKOUT5_PHASE(RXCLK_PHASE/4),
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.DIVCLK_DIVIDE(1.0),
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.REF_JITTER1(0.01),
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.STARTUP_WAIT("FALSE")
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) pll_rx
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(
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.CLKOUT0(),
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.CLKOUT1(),
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.CLKOUT2(),
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.CLKOUT3(),
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.CLKOUT4(rx_lclk_i),
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.CLKOUT5(rx_lclk_div4_i),
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.PWRDWN(1'b0),
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.RST(pll_reset),
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.CLKFBIN(lclk_fb_in),//lclk_fb_in
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.CLKFBOUT(lclk_fb_out),
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.CLKIN1(rx_clkin),
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(7'b0),
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.DCLK(1'b0),
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.DEN(1'b0),
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.DI(16'b0),
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.DWE(1'b0),
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.DRDY(),
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.DO(),
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.LOCKED(lclk_locked)
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);
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//Rx clock buffers
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BUFG rx_lclk_bufg_i(.I(rx_lclk_i), .O(rx_lclk)); //goes to erx_io
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BUFG rx_lclk_div4_bufg_i(.I(rx_lclk_div4_i), .O(rx_lclk_div4)); //goes to erx_io
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//Feedback buffers
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BUFG lclk_fb_bufg_i0(.I(rx_lclk), .O(lclk_fb_in)); //.I(lclk_fb_in),
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//###########################
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// CCLK
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//###########################
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//CCLK differential buffer
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OBUFDS cclk_obuf (.O (e_cclk_p),
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.OB (e_cclk_n),
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.I (cclk_oddr)
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);
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//CCLK oddr
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"),
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.SRTYPE("ASYNC"))
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oddr_lclk (
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.Q (cclk_oddr),
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.C (cclk_bufio),
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.CE (1'b1),
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.D1 (1'b1),
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.D2 (1'b0),
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.R (1'b0),
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.S (1'b0));
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//CCLK bufio
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BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_i));
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//###########################
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// Idelay controller
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//###########################
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(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
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IDELAYCTRL idelayctrl_inst
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(
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.RDY(idelay_ready), // check ready flag in reset sequence?
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.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
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.RST(idelay_reset));
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`endif // `ifdef TARGET_XILINX
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endmodule // eclocks
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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Contributed by Gunnar Hillerstrom
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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